79 lines
1.9 KiB
Verilog
79 lines
1.9 KiB
Verilog
module spiOverJtag ();
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wire tdi, tdo, tck;
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wire [8:0] ir_in;
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wire vs_cdr, vs_sdr, vs_uir;
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sld_virtual_jtag #(.sld_auto_instance_index("YES"),
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.sld_instance_index(0), .sld_ir_width (9)
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) jtag_ctrl (
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.tdi(tdi), .tdo(tdo), .tck(tck), .ir_in(ir_in),
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.virtual_state_cdr(vs_cdr), .virtual_state_sdr(vs_sdr),
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.virtual_state_uir(vs_uir));
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wire spi_csn, spi_si, spi_clk, spi_so;
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altserial_flash_loader #(
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`ifdef cyclone10lp
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.INTENDED_DEVICE_FAMILY ("Cyclone 10 LP"),
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`elsif cycloneive
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.INTENDED_DEVICE_FAMILY ("Cyclone IV E"),
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`elsif cyclonev
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.INTENDED_DEVICE_FAMILY ("Cyclone V"),
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`elsif stratixv
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.INTENDED_DEVICE_FAMILY ("Stratix V"),
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`endif
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.ENHANCED_MODE (1),
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.ENABLE_SHARED_ACCESS ("ON"),
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.ENABLE_QUAD_SPI_SUPPORT (0),
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.NCSO_WIDTH (1)
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) serial_flash_loader (
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.dclkin(spi_clk), .scein(spi_csn), .sdoin(spi_si), .data0out(spi_so),
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.data_in(), .data_oe(), .data_out(), .noe(1'b0),
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.asmi_access_granted (1'b1), .asmi_access_request ()
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);
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/* vs_uir is used to send
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* command to the flash
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* and number of byte to generate
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*/
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reg [7:0] spi_cmd_s;
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reg sdr_d, cdr_d;
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always @(negedge tck) begin
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if (vs_uir) begin
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spi_cmd_s <= ir_in[7:0];
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end
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/* virtual state are updated on rising edge
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* and sampled at falling edge
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* => latch on negedge to use after on falling
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*/
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sdr_d <= vs_sdr;
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cdr_d <= vs_cdr;
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end
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/* data in vs_sdr must be sampled on
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* rising edge but use state dealyed by
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* 1/2 clock cycle
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*/
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reg [7:0] test_s;
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reg tdi_d0_s;
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always @(posedge tck) begin
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if (cdr_d) begin
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test_s <= spi_cmd_s;
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end else if (sdr_d) begin
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test_s <= {tdi, test_s[7:1]};
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end
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tdi_d0_s <= tdi;
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end
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reg spi_si_d;
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always @(negedge tck) begin
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if (vs_sdr | sdr_d)
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spi_si_d <= test_s[0];
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end
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assign spi_csn = !sdr_d;
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assign spi_si = (sdr_d) ? spi_si_d : 1'b0;
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assign spi_clk = sdr_d ? tck : 1'b0;
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assign tdo = sdr_d ? spi_so : tdi_d0_s;
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endmodule
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