184 changed files with 1097 additions and 7136 deletions
--- a/.github/workflows/Test.yml
+++ b/.github/workflows/Test.yml
@ -14,7 +14,7 @@ jobs:
    steps:

    - name: '🧰 Checkout'
-      uses: actions/checkout@v4
+      uses: actions/checkout@v2

    - name: '📓 BuildTheDocs (BTD)'
      uses: buildthedocs/btd@v0
@ -27,7 +27,7 @@ jobs:
      run: sudo rm -rf doc/_build/html/.git

    - name: '📤 Upload artifact: HTML'
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@v2
      with:
        name: openFPGALoader-Documentation
        path: doc/_build/html
@ -38,14 +38,14 @@ jobs:
      fail-fast: false
      matrix:
        os:
+        - 20
        - 22
-        - 24
    name: '🚧🐧 Ubuntu ${{ matrix.os }} | build'
    runs-on: ubuntu-${{ matrix.os }}.04
    steps:

    - name: '🧰 Checkout'
-      uses: actions/checkout@v4
+      uses: actions/checkout@v2

    - name: '⚙️ Install dependencies'
      run: |
@ -55,7 +55,7 @@ jobs:
          gzip \
          libftdi1-2 \
          libftdi1-dev \
-          libhidapi-libusb0 \
+          libhidapi-hidraw0 \
          libhidapi-dev \
          libudev-dev \
          pkg-config \
@ -80,7 +80,7 @@ jobs:
        tar -cvzf ../ubtuntu${{ matrix.os }}.04-openFPGALoader.tgz -C dist .

    - name: '📤 Upload artifact: tarball'
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@v2
      with:
        name: ubtuntu${{ matrix.os }}.04-openFPGALoader
        path: ubtuntu${{ matrix.os }}.04-openFPGALoader.tgz
@ -101,7 +101,7 @@ jobs:
    steps:

    - name: '🧰 Checkout'
-      uses: actions/checkout@v4
+      uses: actions/checkout@v2

    - name: '⚙️ Install dependencies'
      run: |
@ -122,8 +122,8 @@ jobs:
      fail-fast: false
      matrix:
        os:
+        - 20
        - 22
-        - 24
    name: '🚦🐧 Ubuntu ${{ matrix.os }} | test'
    runs-on: ubuntu-${{ matrix.os }}.04
    steps:
@ -133,12 +133,12 @@ jobs:
        sudo apt update -qq
        sudo apt install -y \
          libftdi1-2 \
-          libhidapi-libusb0 \
+          libhidapi-hidraw0 \
          udev \
          zlib1g

    - name: '📥 Download artifact: package'
-      uses: actions/download-artifact@v4.1.7
+      uses: actions/download-artifact@v2
      with:
        name: ubtuntu${{ matrix.os }}.04-openFPGALoader

@ -158,7 +158,7 @@ jobs:
      jobs: ${{ steps.matrix.outputs.jobs }}
    steps:
    - id: matrix
-      uses: msys2/setup-msys2/matrix@a5d2c5a565c520efa5f477391e4e3f87c2e08f46
+      uses: msys2/setup-msys2/matrix@main
      with:
        systems: >-
          mingw64
@ -167,7 +167,7 @@ jobs:

  win:
    needs: win-jobs
-    uses: msys2/setup-msys2/.github/workflows/PKGBUILD.yml@a5d2c5a565c520efa5f477391e4e3f87c2e08f46
+    uses: msys2/setup-msys2/.github/workflows/PKGBUILD.yml@main
    with:
      name: openFPGALoader
      matrix: ${{ needs.win-jobs.outputs.jobs }}
@ -187,7 +187,7 @@ jobs:
    steps:

    - name: '📥 Download artifacts'
-      uses: actions/download-artifact@v4.1.7
+      uses: actions/download-artifact@v2
      with:
        path: artifact

--- a/99-openfpgaloader.rules
+++ b/99-openfpgaloader.rules
@ -24,7 +24,6 @@ ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="664", GROUP="plugdev",

 # anlogic cable
 ATTRS{idVendor}=="0547", ATTRS{idProduct}=="1002", MODE="664", GROUP="plugdev", TAG+="uaccess"
-ATTRS{idVendor}=="336c", ATTRS{idProduct}=="1002", MODE="664", GROUP="plugdev", TAG+="uaccess"

 # altera usb-blaster
 ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev", TAG+="uaccess"
@ -36,9 +35,6 @@ ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="664", GROUP="plugdev",
 # altera usb-blasterII - initialized
 ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev", TAG+="uaccess"

-# altera usb-blasterIII
-ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6022", MODE="664", GROUP="plugdev", TAG+="uaccess"
-
 # dirtyJTAG
 ATTRS{idVendor}=="1209", ATTRS{idProduct}=="c0ca", MODE="664", GROUP="plugdev", TAG+="uaccess"

@ -54,19 +50,10 @@ ATTRS{idVendor}=="0d28", ATTRS{idProduct}=="0204", MODE="664", GROUP="plugdev",
 # icebreaker bitsy
 ATTRS{idVendor}=="1d50", ATTRS{idProduct}=="6146", MODE="664", GROUP="plugdev", TAG+="uaccess"

-# Radiona ULX3S/ULX4M (DFU)
-ATTRS{idVendor}=="1d50", ATTRS{idProduct}=="614b", MODE="664", GROUP="plugdev", TAG+="uaccess"
-
-# numato systems
-ATTRS{idVendor}=="2a19", ATTRS{idProduct}=="1009", MODE="644", GROUP="plugdev", TAG+="uaccess"
-
 # orbtrace-mini dfu
 ATTRS{idVendor}=="1209", ATTRS{idProduct}=="3442", MODE="664", GROUP="plugdev", TAG+="uaccess"

 # QinHeng Electronics USB To UART+JTAG (ch347)
 ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="55dd", MODE="664", GROUP="plugdev", TAG+="uaccess"

-# ESP32-S3 (usb-jtag bridge)
-ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1001", MODE="664", GROUP="plugdev", TAG+="uaccess"
-
 LABEL="openfpgaloader_rules_end"
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -1,8 +1,9 @@
 cmake_minimum_required(VERSION 3.5)

 # set the project name
-project(openFPGALoader VERSION "1.0.0" LANGUAGES CXX)
+project(openFPGALoader VERSION "0.12.0" LANGUAGES CXX)
 add_definitions(-DVERSION=\"v${PROJECT_VERSION}\")
+
 option(ENABLE_OPTIM "Enable build with -O3 optimization level" ON)
 option(BUILD_STATIC "Whether or not to build with static libraries" OFF)
 if (${CMAKE_SYSTEM_NAME} MATCHES "Windows")
@ -11,7 +12,6 @@ else()
 	option(ENABLE_UDEV "use udev to search JTAG adapter from /dev/xx" ON)
 endif()
 option(ENABLE_CMSISDAP "enable cmsis DAP interface (requires hidapi)" ON)
-option(ENABLE_GOWIN_GWU2X "enable Gowin GWU2X interface" ON)
 if (${CMAKE_SYSTEM_NAME} MATCHES "Linux")
 	option(ENABLE_LIBGPIOD "enable libgpiod bitbang driver (requires libgpiod)" ON)
 	option(ENABLE_REMOTEBITBANG "enable remote bitbang driver" ON)
@ -28,7 +28,7 @@ set(ISE_PATH "/opt/Xilinx/14.7" CACHE STRING "ise root directory (default: /opt/
 set(CMAKE_CXX_STANDARD 11)
 set(CMAKE_CXX_STANDARD_REQUIRED True)
 set(CMAKE_CXX_FLAGS_DEBUG "-g -Wall -Wextra ${CMAKE_CXX_FLAGS_DEBUG}")
-if(ENABLE_OPTIM AND NOT(CMAKE_BUILD_TYPE STREQUAL "Debug"))
+if (ENABLE_OPTIM)
 	set(CMAKE_CXX_FLAGS "-O3 ${CMAKE_CXX_FLAGS}")
 endif()

@ -48,10 +48,10 @@ if (USE_PKGCONFIG)
 	find_package(PkgConfig REQUIRED)
 	pkg_check_modules(LIBFTDI REQUIRED libftdi1)
 	pkg_check_modules(LIBUSB REQUIRED libusb-1.0)
-	pkg_check_modules(HIDAPI hidapi-libusb)
-	# if libusb not found try with hidraw
+	pkg_check_modules(HIDAPI hidapi-hidraw)
+	# if hidraw not found try with libusb
 	if (NOT HIDAPI_FOUND)
-		pkg_check_modules(HIDAPI hidapi-hidraw)
+		pkg_check_modules(HIDAPI hidapi-libusb)
 	endif()
 	if (NOT HIDAPI_FOUND)
 		pkg_check_modules(HIDAPI hidapi)
@ -100,6 +100,7 @@ set(OPENFPGALOADER_SOURCE
 	src/efinix.cpp
 	src/efinixHexParser.cpp
 	src/fx2_ll.cpp
+	src/ice40.cpp
 	src/ihexParser.cpp
 	src/pofParser.cpp
 	src/rawParser.cpp
@ -108,6 +109,8 @@ set(OPENFPGALOADER_SOURCE
 	src/usbBlaster.cpp
 	src/epcq.cpp
 	src/svf_jtag.cpp
+	src/jedParser.cpp
+	src/feaparser.cpp
 	src/display.cpp
 	src/jtag.cpp
 	src/ftdiJtagBitbang.cpp
@ -115,10 +118,12 @@ set(OPENFPGALOADER_SOURCE
 	src/configBitstreamParser.cpp
 	src/ftdipp_mpsse.cpp
 	src/main.cpp
+	src/latticeBitParser.cpp
 	src/libusb_ll.cpp
 	src/gowin.cpp
 	src/device.cpp
 	src/jlink.cpp
+	src/lattice.cpp
 	src/progressBar.cpp
 	src/fsparser.cpp
 	src/mcsParser.cpp
@ -129,7 +134,6 @@ set(OPENFPGALOADER_SOURCE
 	src/xilinxMapParser.cpp
 	src/colognechip.cpp
 	src/colognechipCfgParser.cpp
-	src/esp_usb_jtag.cpp
 )

 set(OPENFPGALOADER_HEADERS
@ -147,6 +151,7 @@ set(OPENFPGALOADER_HEADERS
 	src/efinix.hpp
 	src/efinixHexParser.hpp
 	src/fx2_ll.hpp
+	src/ice40.hpp
 	src/ihexParser.hpp
 	src/pofParser.hpp
 	src/progressBar.hpp
@ -162,6 +167,8 @@ set(OPENFPGALOADER_HEADERS
 	src/fsparser.hpp
 	src/part.hpp
 	src/board.hpp
+	src/jedParser.hpp
+	src/feaparser.hpp
 	src/display.hpp
 	src/mcsParser.hpp
 	src/ftdipp_mpsse.hpp
@ -175,30 +182,12 @@ set(OPENFPGALOADER_HEADERS
 	src/gowin.hpp
 	src/cable.hpp
 	src/ftdispi.hpp
+	src/lattice.hpp
+	src/latticeBitParser.hpp
 	src/xilinx.hpp
 	src/xilinxMapParser.hpp
 	src/colognechip.hpp
 	src/colognechipCfgParser.hpp
-	src/esp_usb_jtag.hpp
-)
-
-# Lattice Drivers / Files parsers.
-list(APPEND OPENFPGALOADER_SOURCE
-	src/ice40.cpp
-	src/lattice.cpp
-	src/latticeSSPI.cpp
-	src/feaparser.cpp
-	src/jedParser.cpp
-	src/latticeBitParser.cpp
-)
-
-list(APPEND OPENFPGALOADER_HEADERS
-	src/ice40.hpp
-	src/lattice.hpp
-	src/latticeSSPI.hpp
-	src/jedParser.hpp
-	src/feaparser.hpp
-	src/latticeBitParser.hpp
 )

 link_directories(
@ -229,16 +218,6 @@ target_link_libraries(openFPGALoader
 	${LIBFTDI_LIBRARIES}
 )

-# Gowin GWU2X JTAG interface
-if(ENABLE_GOWIN_GWU2X)
-	target_sources(openFPGALoader PRIVATE src/gwu2x_jtag.cpp)
-	list (APPEND OPENFPGALOADER_HEADERS src/gwu2x_jtag.hpp)
-	add_definitions(-DENABLE_GOWIN_GWU2X=1)
-	message("Gowin GWU2X support enabled")
-else()
-	message("Gowin GWU2X support disabled")
-endif()
-
 if (${CMAKE_SYSTEM_NAME} MATCHES "Windows")
 	# winsock provides ntohs
 	target_link_libraries(openFPGALoader ws2_32)
--- a/README.md
+++ b/README.md
@ -49,7 +49,7 @@ openFPGALoader -c cmsisdap fpga_bitstream.bit
 ## Usage

 ```
-Usage: ./openFPGALoader [OPTION...] BIT_FILE
+Usage: openFPGALoader [OPTION...] BIT_FILE
 openFPGALoader -- a program to flash FPGA

      --altsetting arg          DFU interface altsetting (only for DFU mode)
@ -61,8 +61,6 @@ openFPGALoader -- a program to flash FPGA
  -B, --bridge arg              disable spiOverJtag model detection by
                                providing bitstream(intel/xilinx)
  -c, --cable arg               jtag interface
-      --status-pin arg          JTAG mode / FTDI: GPIO pin number to use as a
-                                status indicator (active low)
      --invert-read-edge        JTAG mode / FTDI: read on negative edge
                                instead of positive
      --vid arg                 probe Vendor ID
@ -73,13 +71,10 @@ openFPGALoader -- a program to flash FPGA
      --ftdi-serial arg         FTDI chip serial number
      --ftdi-channel arg        FTDI chip channel number (channels 0-3 map to
                                A-D)
-  -d, --device arg              device to use (/dev/ttyUSBx)
-      --detect                  detect FPGA, add -f to show connected flash
+      --detect                  detect FPGA
      --dfu                     DFU mode
      --dump-flash              Dump flash mode
      --bulk-erase              Bulk erase flash
-      --enable-quad             Enable quad mode for SPI Flash
-      --disable-quad            Disable quad mode for SPI Flash
      --target-flash arg        for boards with multiple flash chips (some
                                Xilinx UltraScale boards), select the target
                                flash: primary (default), secondary or both
@ -89,13 +84,11 @@ openFPGALoader -- a program to flash FPGA
                                with dump-flash
      --file-type arg           provides file type instead of let's deduced
                                by using extension
-      --flash-sector arg        flash sector (Lattice and Altera MAX10 parts
-                                only)
+      --flash-sector arg        flash sector (Lattice parts only)
      --fpga-part arg           fpga model flavor + package
      --freq arg                jtag frequency (Hz)
  -f, --write-flash             write bitstream in flash (default: false)
      --index-chain arg         device index in JTAG-chain
-      --misc-device arg         add JTAG non-FPGA devices <idcode,irlen,name>
      --ip arg                  IP address (XVC and remote bitbang client)
      --list-boards             list all supported boards
      --list-cables             list all supported cables
@ -103,8 +96,7 @@ openFPGALoader -- a program to flash FPGA
  -m, --write-sram              write bitstream in SRAM (default: true)
  -o, --offset arg              Start address (in bytes) for read/write into
                                non volatile memory (default: 0)
-      --pins arg                pin config TDI:TDO:TCK:TMS or
-                                MOSI:MISO:SCK:CS[:HOLDN:WPN]
+      --pins arg                pin config TDI:TDO:TCK:TMS
      --probe-firmware arg      firmware for JTAG probe (usbBlasterII)
      --protect-flash arg       protect SPI flash area
      --quiet                   Produce quiet output (no progress bar)
@ -121,15 +113,10 @@ openFPGALoader -- a program to flash FPGA
                                1:verbose, 2:debug
  -h, --help                    Give this help list
      --verify                  Verify write operation (SPI Flash only)
-      --xvc                     Xilinx Virtual Cable Functions
      --port arg                Xilinx Virtual Cable and remote bitbang Port
                                (default 3721)
      --mcufw arg               Microcontroller firmware
      --conmcu                  Connect JTAG to MCU
-  -D, --read-dna                Read DNA (Xilinx FPGA only)
-  -X, --read-xadc               Read XADC (Xilinx FPGA only)
-      --read-register arg       Read Status Register(Xilinx FPGA only)
-      --user-flash arg          User flash file (Gowin LittleBee FPGA only)
  -V, --Version                 Print program version

 Mandatory or optional arguments to long options are also mandatory or optional
@ -155,7 +142,3 @@ OPENFPGALOADER_SOJ_DIR=/somewhere openFPGALoader xxxx

 `OPENFPGALOADER_SOJ_DIR` must point to directory containing **spiOverJtag**
 bitstreams.
-
-## Sponsors/Partners
-
-![Sponsors](https://github.com/user-attachments/assets/cb4efce1-ed0c-461c-bd05-9caeb440870d)
--- a/doc/FPGAs.yml
+++ b/doc/FPGAs.yml
@ -1,16 +1,14 @@
 Anlogic:

  - Description: EG4
-    Model:
-      - EG4D20
-      - EG4S20
-    URL: https://www.anlogic.com/en/product/fpga/saleagle/eg4
+    Model: S20
+    URL: http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3
    Memory: OK
    Flash: AS

  - Description: SALELF 2
    Model: EF2M45
-    URL: https://www.anlogic.com/en/product/fpga/salelf/salelf2
+    URL: http://www.anlogic.com/prod_view.aspx?TypeId=12&Id=170&FId=t3:12:3
    Memory: OK
    Flash: OK

@ -33,17 +31,13 @@ Cologne Chip:
 Efinix:

  - Description: Trion
-    Model:
-      - T8
-      - T13
+    Model: T8
    URL: https://www.efinixinc.com/products-trion.html
    Memory: NA
    Flash: OK

  - Description: Titanium
-    Model:
-      - Ti60
-      - Ti180
+    Model: Ti60
    URL: https://www.efinixinc.com/products-titanium.html
    Memory: NA
    Flash: OK
@ -51,7 +45,7 @@ Efinix:

 Gowin:

-  - Description: LittleBee (GW1N)
+  - Description: GW1N
    Model:
     - GW1N-1
     - GW1N-4
@ -60,43 +54,17 @@ Gowin:
     - GW1NS-2C
     - GW1NSR-4C
     - GW1NZ-1
-    URL: https://www.gowinsemi.com/en/product/detail/46/
-    Memory: OK
-    Flash: IF
-
-  - Description: Arora (GW2A)
-    Model:
     - GW2A-18C
-     - GW2A-55
-    URL: https://www.gowinsemi.com/en/product/detail/38/
-    Memory: OK
-    Flash: EF
-
-  - Description: Arora V (GW5A)
-    Model:
-     - GW5A-25
     - GW5AST-138
-     - GW5AT-60
     - GW5AT-138
-    URL: https://www.gowinsemi.com/en/product/detail/60/
+     - GW5A-25
+    URL: https://www.gowinsemi.com/en/product/detail/2/
    Memory: OK
-    Flash: EF
+    Flash: IF / EF


 Intel:

-  - Description: Max II(CPLD)
-    Model: EPM240T100C5N
-    URL: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/max-ii-support.html
-    Memory: OK
-    Flash: OK
-
-  - Description: Cyclone II
-    Model: EP2C5T144C8N
-    URL: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/cyclone-ii-support.html
-    Memory: OK
-    Flash: OK
-    
  - Description: Cyclone III
    Model: EP3C16
    URL: https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html
@ -111,13 +79,6 @@ Intel:
    Memory: OK
    Flash: OK

-  - Description: Cyclone IV GX
-    Model:
-      - EP4CGX150
-    URL: https://www.intel.com/content/www/us/en/products/details/fpga/cyclone/iv/gx/products.html
-    Memory: OK
-    Flash: OK
-
  - Description: Cyclone V E
    Model:
      - 5CEA2
@ -136,13 +97,6 @@ Intel:
    URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
    Memory: OK
    Flash: NT
-  
-  - Description: Stratix V GS
-    Model:
-      - 5SGSD5
-    URL: https://www.intel.de/content/www/de/de/products/sku/210318/stratix-v-5sgsd5-fpga/specifications.html
-    Memory: OK
-    Flash: OK

  - Description: Cyclone 10 LP
    Model: 10CL025
@ -151,12 +105,10 @@ Intel:
    Flash: OK

  - Description: Max 10
-    Model: 
-      - 10M02
-      - 10M08
+    Model: 10M08
    URL: https://www.intel.fr/content/www/fr/fr/products/details/fpga/max/10.html
    Memory: SVF
-    Flash: POF
+    Flash: SVF


 Lattice:
@ -179,12 +131,6 @@ Lattice:
    Memory: OK
    Flash: OK

-  - Description: ECP3
-    Model: LFE3-70E
-    URL: https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3
-    Memory: OK
-    Flash: TBD
-
  - Description: ECP5
    Model:
      - LFE5U-12
@ -268,7 +214,6 @@ Xilinx:
      - xc7k325t
      - xc7k410t
      - xc7k420t
-      - xc7k480t
    URL: https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable
    Memory: OK
    Flash: OK
@ -292,7 +237,6 @@ Xilinx:

  - Description: Artix UltraScale+
    Model:
-      - xcau15p
      - xcau25p
    URL: https://www.xilinx.com/products/silicon-devices/fpga/artix-ultrascale-plus.html
    Memory: OK
@ -306,15 +250,7 @@ Xilinx:
      - xcku115
    URL: https://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale.html#productTable
    Memory: OK
-    Flash: OK (primary)
-
-  - Description: Kintex UltraScale+
-    Model:
-      - xcku3p
-      - xcku5p
-    URL: https://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale-plus.html#productTable
-    Memory: OK
-    Flash: OK
+    Flash: NA

  - Description: Virtex 6
    Model:
@ -323,13 +259,6 @@ Xilinx:
    Memory: OK
    Flash: OK

-  - Description: Virtex UltraScale
-    Model:
-      - xcvu095
-    URL: https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga/virtex-ultrascale.html#productTable
-    Memory: OK
-    Flash: TBD
-
  - Description: Virtex UltraScale+
    Model:
      - xcvu9p
@ -337,13 +266,6 @@ Xilinx:
    Memory: OK
    Flash: OK

-  - Description: Spartan UltraScale+
-    Model:
-      - xcsu35p
-    URL: https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga/spartan-ultrascale-plus.html#productTable
-    Memory: OK
-    Flash: TBD
-
  - Description: Spartan 3
    Model:
      - xc3s200
@ -358,7 +280,6 @@ Xilinx:
      - xc6slx16
      - xc6slx25
      - xc6slx45
-      - xc6slx45T
      - xc6slx150T
    URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html
    Memory: OK
--- a/doc/boards.yml
+++ b/doc/boards.yml
@ -1,7 +1,7 @@
 - ID: ac701
  Description: Xilinx Artix-7 FPGA AC701 Evaluation Kit
  URL: https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html
-  FPGA: Artix xc7a200tfbg676
+  FPGA: Artix xc7a200t2fbg676c
  Memory: OK
  Flash: NT
  Constraints: AC701
@ -13,20 +13,6 @@
  Memory: OK
  Flash: OK

- ID: alinx_ax7201
-  Description: AX7201 FPGA Dev Board & Kit with AMD Artix 7
-  URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Artix-7/AX7201.html
-  FPGA: Artix xc7a200tsbg484
-  Memory: OK
-  Flash: OK
-
- ID: alinx_ax7203
-  Description: AX7203 FPGA Dev Board & Kit with AMD Artix 7
-  URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Artix-7/AX7203.html
-  FPGA: Artix xc7a200tfbg484
-  Memory: OK
-  Flash: OK
-
 - ID: litex-acorn-baseboard-mini
  Description: The LiteX-Acorn-Baseboards are baseboards developed around the SQRL's Acorn board (or Nite/LiteFury)
  URL: https://github.com/enjoy-digital/litex-acorn-baseboard/
@ -279,13 +265,6 @@
  Memory: OK
  Flash: OK

- ID: cyc5000
-  Description: Trenz CYC5000
-  URL: https://shop.trenz-electronic.de/en/TEI0050-01-AAH13A-CYC5000-with-Cyclone-V-FPGA-25kLE-8-MByte-SDRAM
-  FPGA: Cyclone V 5CEBA2U15C8
-  Memory: OK
-  Flash: OK
-
 - ID: c10lp-refkit
  Description: Trenz c10lp-refkit
  URL: https://shop.trenz-electronic.de/en/TEI0009-02-055-8CA-Cyclone-10-LP-RefKit-10CL055-Development-Board-32-MByte-SDRAM-16-MByte-Flash
@ -344,13 +323,6 @@
  FPGA: MAX 10 10M50DAF484C6GES
  Memory: OK

- ID: dragonL
-  Description: KNJN Dragon-L PCI Express & HDMI FPGA board
-  URL: https://www.knjn.com/FPGA-Dragon-L.html
-  FPGA: Spartan6 xc6slx25Tcsg324
-  Memory: OK
-  Flash: OK
-
 - ID: ecp5_evn
  Description: Lattice ECP5 5G Evaluation Board
  URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard
@ -401,13 +373,6 @@
  Memory: OK
  Flash: NA

- ID: hyvision_opt01
-  Description: HyVision PCIe OPT01 rev.F
-  URL: NA
-  FPGA: Kintex7 xc7k70tfbg676
-  Memory: OK
-  Flash: OK
-
 - ID: honeycomb
  Description: honeycomb
  URL: https://github.com/Disasm/honeycomb-pcb
@ -488,13 +453,6 @@
  Flash: AS
  Constraints: IceZumAlhambraII

- ID: icepi-zero
-  Description: Icepi Zero
-  URL: https://github.com/cheyao/icepi-zero
-  FPGA: ECP5 LFE5U
-  Memory: OK
-  Flash: OK
-
 - ID: kc705
  Description: Xilinx KC705
  URL: https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
@ -508,7 +466,7 @@
  URL: https://www.xilinx.com/products/boards-and-kits/kcu105.html
  FPGA: Kintex UltraScale xcku040-ffva1156
  Memory: OK
-  Flash: OK (primary and secondary)
+  Flash: OK

 - ID: kcu116
  Description: Xilinx KCU116
@ -538,13 +496,6 @@
  Memory: OK
  Flash: OK

- ID: lilygo-t-fpga
-  Description: Lilygo T-FPGA
-  URL: https://www.lilygo.cc/products/t-fpga
-  FPGA: Gowin GW1NSR-LV4CQN48PC6/15
-  Memory: OK
-  Flash: OK
-
 - ID: machXO2EVN
  Description: Lattice MachXO2 Breakout Board Evaluation Kit
  URL: https://www.latticesemi.com/products/developmentboardsandkits/machxo2breakoutboard
@ -566,13 +517,6 @@
  Memory: OK
  Flash: OK

- ID: mlk-s200-eg4d20
-  Description: MILIANKE S200 EG4D20 Development Board
-  URL: https://www.milianke.com/product-item-108.html
-  FPGA: eagle s20 EG4D20EG176
-  Memory: OK
-  Flash: OK
-
 - ID: mini_itx
  Description: Avnet Mini-ITX Base Kit
  URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/mini-itx/
@ -580,13 +524,6 @@
  Memory: OK
  Flash: NA

- ID: mimas_a7
-  Description: Numato Systems Mimas A7
-  URL: https://numato.com/product/mimas-a7-artix-7-fpga-development-board/
-  FPGA: Artix xc7a50tfgg484
-  Memory: OK
-  Flash: OK
-
 - ID: nexys_a7_50
  Description: Digilent Nexys A7(Nexys 4 DDR)
  URL: https://digilent.com/reference/programmable-logic/nexys-a7/start
@ -624,13 +561,6 @@
  Memory: OK
  Flash: NT

- ID: opensourceSDRLabKintex7
-  Description: Open Source SDR Lab Kintex-7 325t FPGA PCIE Development Board
-  URL: https://opensourcesdrlab.com/products/fpga-xilinx-kintex-7-xc7k325t-pcie-development-board-with-dual-gigabit-ethernet-ports-dual-10-gigabit-sfp-optical-communication
-  FPGA: Kintex7 xc7k325tffg676
-  Memory: OK
-  Flash: OK
-
 - ID: orbtrace_dfu
  Description: ORBTrace mini (dfu mode)
  URL: https://store.zyp.no/product/orbtrace-mini
@ -744,13 +674,6 @@
  Memory: OK
  Flash: NA

- ID: SPEC45
-  Description: CERN Simple PCIe FMC carrier SPEC
-  URL: https://ohwr.org/project/spec150/wikis/home
-  FPGA: Spartan6 xc6slx45Tfgg484
-  Memory: OK
-  Flash: OK
-
 - ID: SPEC150
  Description: CERN Simple PCIe FMC carrier SPEC
  URL: https://ohwr.org/project/spec150/wikis/home
@ -765,13 +688,6 @@
  Memory: OK
  Flash: OK

- ID: tangconsole
-  Description: Sipeed Tang Console (dock board for Tang Mega 60k or 138k SOM)
-  URL: https://wiki.sipeed.com/hardware/en/tang/tang-console/mega-console.html
-  FPGA: Gowin Arora V GW5AT-60 / GW5AT-138
-  Memory: OK
-  Flash: OK
-
 - ID: tangnano
  Description: Sipeed Tang Nano
  URL: https://tangnano.sipeed.com/en/
@ -902,13 +818,6 @@
  Memory: NA
  Flash: OK

- ID: ulx4m_dfu
-  Description: Radiona ULX4M LD/LS DFU mode
-  URL: https://github.com/intergalaktik/ulx4m-ls
-  FPGA: ECP5 LFE5U
-  Memory: NA
-  Flash: OK
-
 - ID: vec_v6
  Description: Xilinx VCU118
  URL: https://vmm-srs.docs.cern.ch/
@ -916,20 +825,6 @@
  Memory: OK
  Flash: OK

- ID: vc709
-  Description: AMD Virtex-7 FPGA VC709 Connectivity Kit
-  URL: https://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html
-  FPGA: Virtex7 xc7vx690tffg1761
-  Memory: OK
-  Flash: NA
-
- ID: vcu108
-  Description: Xilinx VCU108
-  URL: https://www.xilinx.com/products/boards-and-kits/vcu108.html
-  FPGA: Virtex UltraScale xcvu095-ffva2104
-  Memory: OK
-  Flash: TBD
-
 - ID: vcu118
  Description: Xilinx VCU118
  URL: https://www.xilinx.com/products/boards-and-kits/vcu118.html
@ -1044,24 +939,3 @@
  FPGA: xc7s50csga324?
  Memory: OK
  Flash: OK
-
- ID: efinix_jtag_ft2232
-  Description: Efinix FT2232 development boards with JTAG on port 2 (Ti180J484 EVK, etc)
-  URL: https://www.efinixinc.com/products-devkits-titaniumti180j484.html
-  FPGA: Titanium Ti180J484 (and others)
-  Memory: OK
-  Flash: NA
-
- ID: step-max10_v1
-  Description: STEP MAX10 V1
-  URL: https://wiki.stepfpga.com/step-max10
-  FPGA: Altera 10M02SCM153C8G
-  Memory: OK
-  Flash: NA
-
- ID: step-mxo2_v2
-  Description: STEP MXO2 V2
-  URL: https://wiki.stepfpga.com/xo2-4000hc
-  FPGA: Lattice LCMXO2-4000HC-4MG132CC
-  Memory: OK
-  Flash: OK
--- a/doc/cable.yml
+++ b/doc/cable.yml
@ -12,13 +12,6 @@ arm-usb-ocd-h:
    URL: https://www.olimex.com/Products/ARM/JTAG/ARM-USB-OCD-H/


-arm-usb-tiny-h:
-
-  - Name: Olimex ARM-USB-TINY-H adapter
-    Description: Low-cost high-speed ARM USB JTAG
-    URL: https://www.olimex.com/Products/ARM/JTAG/ARM-USB-TINY-H/
-
-
 bus_blaster:

  - Name: Dangerousprototypes Bus Blaster
@ -74,13 +67,6 @@ gatemate_evb_spi:
    URL: https://colognechip.com/programmable-logic/gatemate/


-gwu2x:
-
-  - Name: gwu2x
-    Description: Gowin GWUX2X
-    URL: https://www.gowinsemi.com/en/product/detail/55/
-
-
 dfu:

  - Name: DFU interface
@ -242,11 +228,6 @@ lpc-link2:
    URL: https://www.nxp.com/design/microcontrollers-developer-resources/lpc-link2:OM13054


-numato:
-
-  - Name: numato
-    Description: Embedded cable for Numato Systems Mimas-A7 board
-    
 orbtrace:

  - Name: orbtrace interface
@ -295,13 +276,6 @@ usb-blasterII:
    URL: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pdf


-usb-blasterIII:
-
-  - Name: intel USB Blaster III interface
-    Description: JTAG programmer cable from intel/altera (FTDI2232 with custom VID/PID)
-    URL: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pdf
-
-
 xvc-client:

  - Name: Xilinx Virtual Cable
--- a/doc/figs/max10_flash-memory.png
+++ b/doc/figs/max10_flash-memory.png
--- a/doc/guide/advanced.rst
+++ b/doc/guide/advanced.rst
@ -34,7 +34,7 @@ Reading the bitstream from STDIN
  .. code-block:: bash

    # FPGA side
-    nc -lp port | openFPGALoader --file-type xxx [option]
+    nc -lp port | openFPGALoader --file-type xxx [option

    # Bitstream side
    nc -q 0 host port < /path/to/bitstream.ext
@ -83,35 +83,6 @@ Writing to an arbitrary address in flash memory
 With FPGA using an external SPI flash (*xilinx*, *lattice ECP5/nexus/ice40*, *anlogic*, *efinix*) option ``-o`` allows
 one to write raw binary file to an arbitrary adress in FLASH.

-Detect/read/write on primary/secondary flash memories
-=====================================================
-
-With FPGA using two external SPI flash (some *xilinx* boards) option ``--target-flash`` allows to select the QSPI chip.
-
-To detect:
-
-.. code-block:: bash
-
-    openFPGALoader -b kcu105 -f --target-flash {primary,secondary} --detect
-
-To read the primary flash memory:
-
-.. code-block:: bash
-
-    openFPGALoader -b kcu105 -f --target-flash primary --dump-flash --file-size N_BYTES mydump.bin
-
-and the second flash memory:
-
-.. code-block:: bash
-
-    openFPGALoader -b kcu105 -f --target-flash secondary --dump-flash --file-size N_BYTES --secondary-bitstream mydump.bin
-
-To write on secondary flash memory:
-
-.. code-block:: bash
-
-    openFPGALoader -b kcu105 -f --target-flash secondary --secondary-bitstream mySecondaryBitstream.bin
-
 Using an alternative directory for *spiOverJtag*
 ================================================

--- a/doc/guide/install.rst
+++ b/doc/guide/install.rst
@ -6,32 +6,6 @@ Installing openFPGALoader
 Linux
 =====

-Debian/Ubuntu
----------
-
-openFPGALoader is available in the default repositories:
-
-.. code-block:: bash
-    
-    sudo apt install openfpgaloader
-
-Guix
----------
-
-openFPGALoader is available in the default repositories:
-
-.. code-block:: bash
-
-    guix install openfpgaloader
-
-To use openFPGALoader under GuixSystem without root privileges it is necessary to install the necessary udev rules. This can be done by extending ``udev-service-type`` in the ``operating-system`` configuration file with this package
-
-.. code-block:: bash
-
-    (udev-rules-service 'openfpgaloader openfpgaloader #:groups '(\"plugdev\")
-
-Additionally, ``plugdev`` group should be registered in the ``supplementary-groups`` field of your ``user-account``declaration.  Refer to ``Base Services`` section in the manual for examples.
-
 Arch Linux
 ----------

@ -59,7 +33,7 @@ openFPGALoader is available as a Copr repository:
    sudo dnf copr enable mobicarte/openFPGALoader
    sudo dnf install openFPGALoader

-From source 
+From source (Debian, Ubuntu)
 ----------------------------

 This application uses ``libftdi1``, so this library must be installed (and, depending on the distribution, headers too):
--- a/doc/guide/troubleshooting.rst
+++ b/doc/guide/troubleshooting.rst
@ -32,13 +32,6 @@ Check your openFPGALoader version:

 If it is older than release then v0.9.0, install the most recent version (from commit `f5b89bff68a5e2147404a895c075773884077438 <https://github.com/trabucayre/openFPGALoader/commit/fe259fb78d185b3113661d04cd7efa9ae0232425>`_ or later).

-Cannot flash Tang Nano 20k (issue `#251 <https://github.com/trabucayre/openFPGALoader/issues/511>`_)
-====================================================================================================
-
-Some firmware version cannot be flashed on Linux-based systems. Version 2024122312 is such an example. It seems this version was not published on the `SiPeed website <https://api.dl.sipeed.com/TANG/Debugger/onboard/BL616/>`_, however some boards sold have this firmware.
-
-The cause of the problem is the debugger on the Tang Nano, specifically the firmware of this debugger. This firmware can be easily updated by following `these <https://wiki.sipeed.com/hardware/en/tang/common-doc/update_debugger.html>`_ steps.
-
 Cannot flash Tang Nano 9k (issue `#251 <https://github.com/trabucayre/openFPGALoader/issues/251>`_)
 ===================================================================================================

@ -49,4 +42,4 @@ Unable to open FTDI device: -4 (usb_open() failed) (issue `#245 <https://github.

 Edit your `/etc/udev/rules.d/99-ftdi.rules` file exchanging your programming device permissions.

-For more information, check the udev section from `this guide <install.rst>`_
+For more information, check the udev section from `this guide <install.rst>`_
--- a/doc/vendors/gowin.rst
+++ b/doc/vendors/gowin.rst
@ -62,17 +62,3 @@ It's possible to flash external SPI Flash (connected to MSPI) in bscan mode by u

  Gowin's FPGA may fails to be detected if **JTAGSEL_N** (pin 08 for *GW1N-4K*) is used as a GPIO.
  To recover you have to pull down this pin (before power up) to recover JTAG interface (*UG292 - JTAGSELL_N section*).
-
-User Flash
----------
-
-.. ATTENTION::
-  User Flash support is based on reverse engineering of the JTAG protocol. This functionality should be considered
-  experimental as it hasn't been thoroughly tested, and may in some circumstances destroy your device.
-
-Gowin FPGA come with extra flash space that can be read and written from the programmable logic ("User Flash"). This
-flash section can also be programmed via the JTAG interface:
-
-.. code-block:: bash
-
-    openFPGALoader --write-flash /path/to/bitstream.fs --user-flash /path/to/flash.bin
--- a/doc/vendors/intel.rst
+++ b/doc/vendors/intel.rst
@ -34,14 +34,6 @@ SVF and RBF files are supported.
  As mentioned in ``cyclone`` handbooks, real-time decompression is not supported by FPGA in JTAG mode.
  Keep in mind to disable this option.

-You can have Quartus automatically generate SVF and RBF files by adding these lines to the ``qsf`` file, or include them in a ``tcl`` file in FuseSoC
-
-.. code-block:: 
-
-    set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
-    set_global_assignment -name GENERATE_RBF_FILE ON
-    set_global_assignment -name GENERATE_SVF_FILE ON
-
 file load:

 .. code-block:: bash
@ -55,13 +47,7 @@ with ``boardname`` = ``de0``, ``cyc1000``, ``c10lp-refkit``, ``de0nano``, ``de0n
 SPI flash
 ---------

-RPD and RBF are supported. POF is only supported for MAX10 (internal flash).
-
-``pof`` to ``rpd``:
-
-.. code-block:: bash
-
-    quartus_cpf -c project_name.pof project_name.rpd
+RPD and RBF are supported.

 ``sof`` to ``rpd``:

@ -81,142 +67,3 @@ file load:
    openFPGALoader -b boardname -r project_name.rbf

 with ``boardname`` = ``cyc1000``, ``c10lp-refkit``.
-
-MAX10: FPGA Programming Guide
-=============================
-
-Supported Boards:
-
-* step-max10_v1
-* analogMax
-
-Supported File Types:
-
-* ``svf``
-* ``pof``
-* ``bin`` (arbitrary binary files)
-
-Internal Flash Organization
---------------------------
-
-The internal flash is divided into five sections:
-
- ``UFM1`` and ``UFM0`` for user data
- ``CFM2``, ``CFM1``, and ``CFM0`` for storing one or two bitstreams
-
-.. image:: ../figs/max10_flash-memory.png
-  :alt: max10 internal flash memory structure
-
-Flash usage depends on the configuration mode. In all modes:
-
- ``CFM0`` is used to store a bitstream
- ``UFM0`` and ``UFM1`` are available for user data
- The remaining ``CFMx`` sections (``CFM1``, ``CFM2``) can be used for
-  additional bitstreams or user data
-
-Using ``svf``
-------------
-
-This method is the **simplest** (and slowest) way to load or write a bitstream.
-
-.. note::
-
-    This method is required to load a bitstream into *SRAM*.
-
-.. code-block:: bash
-
-    openFPGALoader [-b boardname] -c cablename the_svf_file.svf
-
-**Parameters:**
-
-* ``boardname``: One of the boards supported by ``openFPGALoader`` (optional).
-* ``cablename``: One of the supported cables (see ``--list-cables``).
-
-Using ``pof``
-------------
-
-To write a bitstream into the internal flash, using a ``pof`` file is the
-**fastest** approach.
-
-.. code-block:: bash
-
-    openFPGALoader [-b boardname] [--flash-sector] -c cablename the_pof_file.pof
-
-**Parameters:**
-
-* ``boardname``: A board supported by ``openFPGALoader`` (optional).
-* ``cablename``: One of the supported cables (see ``--list-cables``).
-* ``--flash-sector``: Optional. Comma-separated list of sectors to update.
-  If omitted, the entire flash is erased and reprogrammed.
-
-Accepted Flash Sectors:
-
-* ``UFM0``, ``UFM1``: User Flash Memory sections.
-* ``CFM0``, ``CFM1``, ``CFM2``: Configuration Flash Memory sectors.
-
-**Example:**
-
-.. code-block:: bash
-
-    openFPGALoader -c usb-blaster --flash-sector UFM1,CFM0,CFM2 the_pof_file.pof
-
-This command updates ``UFM1``, ``CFM0``, and ``CFM2``, leaving all other
-sectors unchanged.
-
-Using an arbitrary binary file
------------------------------
-
-Unlike Altera Quartus, it supports any binary format without limitations
-(not limited to a ``.bin``).
-With this feature, it's not required to provides the file at gateware build
-time: it may be updated at any time without gateware modification/rebuild.
-
-.. note:: This approach is useful to updates, for example, a softcore CPU firmware.
-
-**Basic usage:**
-
-.. code-block:: bash
-
-    openFPGALoader [-b boardname] -c cablename [--offset $OFFSET] the_bin_file.bin
-
-* ``boardname``: a boards supported by ``openFPGALoader`` (optional).
-* ``cablename``: One of the supported cables (see ``--list-cables``).
-* ``$OFFSET``: To start writing ``$OFFSET`` bytes after *User Flash memory*
-  start address (optional, default: 0x00).
-
-This command erases and writes the contents of ``the_bin_file.bin`` into
-``UFM1`` and ``UFM0``. If ``--offset`` is specified, the binary content is
-written starting from that offset.
-
-Depending on the max10 configuration mode (see picture), it's possible to
-extend *User Flash Memory* area by using `CFM2` and `CFM1`. This is not the
-default behavior and user must explictly change this by using
-`--flash-sector` argument:
-
-* ``--flash-sector UFMx`` or ``--flash-sector CFMy`` (with x= 1 or 0 and
-  y = 2 or 1) to specify only one sector
-* ``--flash-sector UFM1,UFM0`` is equivalent to the default behavior
-* ``--flash-sector UFM1,CFM2`` to erase and update ``UFM1``, ``UFM0``
-  and ``CFM2`` (equivalent to ``--flash-sector UFM1,UFM0,CFM2``)
-
-Intel/Altera (Old Boards)
-=========================
-
-.. NOTE::
-
-  * Cyclone II (FPGA) (Tested OK: EP2C5T144C8N)
-  * Max II (CPLD) (Tested OK: EPM240T100C5N)
-
-Loading a Serial Vector Format (.svf)
-------------------------------------
-
-SVF files are supported.
-
-To load the file:
-
- .. code-block:: bash
-
-    openFPGALoader -c usb-blaster project_name.svf
-
- 
- 
--- a/doc/vendors/lattice.rst
+++ b/doc/vendors/lattice.rst
@ -73,8 +73,8 @@ Bin file load:

 Since it's a direct access to the flash (SPI) the ``-b`` option is required.

-ECP5/ECP3/Certus-NX/CertusPro-NX/Crosslink-NX
-=============================================
+ECP5/Crosslink-NX
+=================

 SRAM
 ----
@ -89,10 +89,6 @@ SRAM
 SPI Flash
 ---------

-.. note::
-
-   SPI Flash write is not supported for ECP3 family.
-
 BIT:

 .. code-block:: bash
--- a/spiOverJtag/.gitignore
+++ b/spiOverJtag/.gitignore
@ -1,6 +1,3 @@
 tmp_*
 *.bit
 *.rbf
-vivado*.jou
-vivado*.log
-.Xil
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@ -1,41 +1,36 @@
 XILINX_PARTS := xc3s500evq100 \
 	xc6slx9tqg144 xc6slx9csg324 \
-	xc6slx16ftg256 xc6slx16csg324 xc6slx25csg324 xc6slx45csg324 xc6slx100fgg484 \
-	xc6slx25tcsg324 xc6slx45tfgg484 xc6slx150tfgg484 xc6slx150tcsg484 \
+	xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
+	xc6slx150tfgg484 xc6slx150tcsg484 \
 	xc6vlx130tff784 \
-	xc7a12t xc7a15t xc7a25t xc7a35t xc7a50t xc7a75t xc7a100t xc7a200t \
-	xc7s6 xc7s15 xc7s25 xc7s50 xc7s75 xc7s100 \
+	xc7a15tcpg236 \
+	xc7a25tcpg238 xc7a25tcsg325 \
+	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \
+	xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \
+	xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
+	xc7a200tsbg484 xc7a200tfbg484 \
+	xc7s25csga225 xc7s25csga324 xc7s50csga324 \
 	xc7k70tfbg484 xc7k70tfbg676 \
 	xc7k160tffg676 \
 	xc7k325tffg676 xc7k325tffg900 \
 	xc7k420tffg901 \
 	xcku3p-ffva676 \
 	xc7vx330tffg1157 \
-	xcku040-ffva1156 xcku060-ffva1156 \
 	xcku5p-ffvb676 \
-	xcvu9p-flga2104 xcvu37p-fsvh2892 \
-	xcau15p-ffvb676
+	xcvu9p-flga2104 xcvu37p-fsvh2892
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

 ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
-	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927 5sgsd5
+	ep4ce2217 ep4ce1523 ep4ce11523 5ce223 5ce423 5ce523 5ce927
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))

-EFINIX_PARTS := t8f81 t13f256 ti180j484
-EFINIX_BIT_FILES := $(addsuffix .bit.gz, $(addprefix spiOverJtag_efinix_, $(EFINIX_PARTS)))
-
-BIT_FILES := $(ALTERA_BIT_FILES) $(EFINIX_BIT_FILES) $(XILINX_BIT_FILES)
+BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)

 all: $(BIT_FILES)

-$(EFINIX_BIT_FILES) : spiOverJtag_efinix_%.bit.gz : tmp_efinix_%/efinix_spiOverJtag.bit
-	gzip -9 -c $< > $@
-tmp_efinix_%/efinix_spiOverJtag.bit : efinix_spiOverJtag.v
-	./efinix_build.py --device $*
-
 $(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit
-
-tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v spiOverJtag_core.v
+	gzip -9 -c $< > $@
+tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v
 	./build.py $*

 $(ALTERA_BIT_FILES): spiOverJtag_%.rbf.gz: tmp_%/spiOverJtag.rbf
--- a/spiOverJtag/altera_spiOverJtag.v
+++ b/spiOverJtag/altera_spiOverJtag.v
@ -19,8 +19,6 @@ module spiOverJtag ();
 		.INTENDED_DEVICE_FAMILY  ("Cyclone IV E"),
 `elsif cyclonev
 		.INTENDED_DEVICE_FAMILY  ("Cyclone V"),
-`elsif stratixv
-		.INTENDED_DEVICE_FAMILY  ("Stratix V"),
 `endif
 		.ENHANCED_MODE           (1),
 		.ENABLE_SHARED_ACCESS    ("ON"),
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@ -1,41 +1,6 @@
 #!/usr/bin/env python3
-
-import os
-import re
-
 from edalize.edatool import get_edatool
-
-packages = {
-    "Artix": {
-        "xc7a12t"  : ["cpg238", "csg325"],
-        "xc7a15t"  : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"],
-        "xc7a25t"  : ["cpg238", "csg325"],
-        "xc7a35t"  : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"],
-        "xc7a50t"  : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"],
-        "xc7a75t"  : ["csg324", "ftg256", "fgg484", "fgg676"],
-        "xc7a100t" : ["csg324", "ftg256", "fgg484", "fgg676"],
-        "xc7a200t" : ["sbg484", "fbg484", "fbg676", "ffg1156"],
-    },
-    # Added but seems not possible to use same bitstream
-    # for all Kintex with the same size but different package.
-    "Kintex 7": {
-        "xc7k70t"  : ["fbg484", "fbg676"],
-        "xc7k160t" : ["fbg484", "fbg676", "ffg676"],
-        "xc7k325t" : ["fbg676", "ffg676", "fbg900", "ffg900"],
-        "xc7k355t" : ["ffg901"],
-        "xc7k410t" : ["fbg676", "ffg676", "fbg900", "ffg900"],
-        "xc7k420t" : ["ffg901", "ffg1156"],
-        "xc7k480t" : ["ffg901", "ffg1156"],
-    },
-    "Spartan 7": {
-        "xc7s6"   : ["ftgb196", "cpga196", "csga225"],
-        "xc7s15"  : ["ftgb196", "cpga196", "csga225"],
-        "xc7s25"  : ["ftgb196", "csga225", "csga324"],
-        "xc7s50"  : ["ftgb196", "csga324", "fgga484"],
-        "xc7s75"  : ["fgga484", "fgga676"],
-        "xc7s100" : ["fgga484", "fgga676"],
-    },
-}
+import os

 if len(os.sys.argv) != 2:
    print("missing board param")
@ -51,12 +16,9 @@ if not os.path.isdir(build_dir):
    else:
        print ("Successfully created the directory %s " % build_dir)

-currDir    = os.path.abspath(os.path.curdir) + '/'
-files      = []
+currDir = os.path.abspath(os.path.curdir) + '/'
+files = []
 parameters = {}
-pkg_name   = None
-pkg        = None
-model      = ""

 subpart = part[0:4].lower()
 if subpart == '10cl':
@ -70,15 +32,9 @@ elif subpart[0:2] == '5c':
    tool = "quartus"
    files.append({'name': currDir + 'constr_cycloneV.tcl',
                  'file_type': 'tclSource'})
-elif subpart[0:2] == '5s':
-    family = "Stratix V"
-    tool = "quartus"
-    files.append({'name': currDir + 'constr_cycloneV.tcl',
-                  'file_type': 'tclSource'})
 elif subpart == "xc7a":
    family = "Artix"
-    tool   = "vivado"
-    model  = subpart
+    tool = "vivado"
 elif subpart == "xc7v":
    family = "Virtex 7"
    tool = "vivado"
@ -91,11 +47,9 @@ elif subpart == "xc7k":
        family = "Kintex7"
        tool = "ise"
    speed = -2
-    model = subpart
 elif subpart == "xc7s":
    family = "Spartan 7"
-    tool   = "vivado"
-    model  = subpart
+    tool = "vivado"
 elif subpart == "xc6s":
    family = "Spartan6"
    tool = "ise"
@ -108,23 +62,13 @@ elif subpart == "xc6v":
    family = "Virtex6"
    tool = "ise"
    speed = -1
-elif subpart in ["xcvu", "xcku", "xcau"]:
+elif subpart in ["xcvu", "xcku"]:
    family = "Xilinx UltraScale"
    tool = "vivado"
 else:
    print("Error: unknown device")
    os.sys.exit()

-if model in ["xc7a", "xc7s"]:
-    pkg      = packages[family][part][0]
-    pkg_name = f"{model}_{pkg}"
-if model in ["xc7k"]:
-    m        = re.match(r"(xc7k\d+t)(\w+)", part)
-    pkg      = m.group(2)
-    pkg_name = f"{model}_{pkg}"
-    if tool == "ise":
-        model = m.group(1)
-
 if tool in ["ise", "vivado"]:
    pkg_name = {
        "xc3s500evq100"    : "xc3s_vq100",
@ -132,23 +76,42 @@ if tool in ["ise", "vivado"]:
        "xc6slx9csg324"    : "xc6s_csg324",
        "xc6slx16ftg256"   : "xc6s_ftg256",
        "xc6slx16csg324"   : "xc6s_csg324",
-        "xc6slx25csg324"   : "xc6s_csg324",
-        "xc6slx25tcsg324"  : "xc6s_t_csg324",
        "xc6slx45csg324"   : "xc6s_csg324",
-        "xc6slx45tfgg484"  : "xc6s_t_fgg484",
        "xc6slx100fgg484"  : "xc6s_fgg484",
        "xc6slx150tcsg484" : "xc6s_csg484",
        "xc6slx150tfgg484" : "xc6s_t_fgg484",
        "xc6vlx130tff784"  : "xc6v_ff784",
+        "xc7a15tcpg236"    : "xc7a_cpg236",
+        "xc7a25tcpg238"    : "xc7a_cpg238",
+        "xc7a25tcsg325"    : "xc7a_csg325",
+        "xc7a35tcpg236"    : "xc7a_cpg236",
+        "xc7a35tcsg324"    : "xc7a_csg324",
+        "xc7a35tftg256"    : "xc7a_ftg256",
+        "xc7a35tfgg484"    : "xc7a_fgg484",
+        "xc7a50tcpg236"    : "xc7a_cpg236",
+        "xc7a50tcsg324"    : "xc7a_csg324",
+        "xc7a50tfgg484"	   : "xc7a_fgg484",
+        "xc7a75tfgg484"    : "xc7a_fgg484",
+        "xc7a100tcsg324"   : "xc7a_csg324",
+        "xc7a100tfgg484"   : "xc7a_fgg484",
+        "xc7a100tfgg676"   : "xc7a_fgg676",
+        "xc7a200tsbg484"   : "xc7a_sbg484",
+        "xc7a200tfbg484"   : "xc7a_fbg484",
+        "xc7k70tfbg484"    : "xc7k_fbg484",
+        "xc7k70tfbg676"    : "xc7k_fbg676",
+        "xc7k160tffg676"   : "xc7k_ffg676",
+        "xc7k325tffg676"   : "xc7k_ffg676",
+        "xc7k325tffg900"   : "xc7k_ffg900",
+        "xc7k420tffg901"   : "xc7k_ffg901",
        "xc7vx330tffg1157" : "xc7v_ffg1157",
-        "xcku040-ffva1156" : "xcku040_ffva1156",
-        "xcku060-ffva1156" : "xcku060_ffva1156",
-        "xcvu9p-flga2104"  : "xcvu9p_flga2104",
+        "xc7s25csga225"    : "xc7s_csga225",
+        "xc7s25csga324"    : "xc7s_csga324",
+        "xc7s50csga324"    : "xc7s_csga324",
+        "xcvu9p-flga2104" : "xcvu9p_flga2104",
        "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
-        "xcku3p-ffva676"   : "xcku3p_ffva676",
-        "xcku5p-ffvb676"   : "xcku5p_ffvb676",
-        "xcau15p-ffvb676"  : "xcau15p_ffvb676",
-    }.get(part, pkg_name)
+        "xcku3p-ffva676" : "xcku3p_ffva676",
+        "xcku5p-ffvb676" : "xcku5p_ffvb676",
+        }[part]
    if tool == "ise":
        cst_type = "UCF"
        tool_options = {'family': family,
@ -158,38 +121,35 @@ if tool in ["ise", "vivado"]:
                            "xc6slx9csg324":    "xc6slx9",
                            "xc6slx16ftg256":   "xc6slx16",
                            "xc6slx16csg324":   "xc6slx16",
-                            "xc6slx25csg324":   "xc6slx25",
-                            "xc6slx25tcsg324":  "xc6slx25t",
                            "xc6slx45csg324":   "xc6slx45",
-                            "xc6slx45tfgg484":  "xc6slx45t",
                            "xc6slx100fgg484":  "xc6slx100",
                            "xc6slx150tcsg484": "xc6slx150t",
                            "xc6slx150tfgg484": "xc6slx150t",
                            "xc6vlx130tff784":  "xc6vlx130t",
-                            }.get(part, model),
+                            "xc7k325tffg676":   "xc7k325t",
+                            "xc7k325tffg900":   "xc7k325t",
+                            "xc7k420tffg901":   "xc7k420t",
+                            }[part],
                        'package': {
                            "xc3s500evq100":    "vq100",
                            "xc6slx9tqg144":    "tqg144",
                            "xc6slx9csg324":    "csg324",
                            "xc6slx16ftg256":   "ftg256",
                            "xc6slx16csg324":   "csg324",
-                            "xc6slx25csg324":   "csg324",
-                            "xc6slx25tcsg324":  "csg324",
                            "xc6slx45csg324":   "csg324",
-                            "xc6slx45tfgg484":  "fgg484",
                            "xc6slx100fgg484":  "fgg484",
                            "xc6slx150tcsg484": "csg484",
                            "xc6slx150tfgg484": "fgg484",
                            "xc6vlx130tff784":  "ff784",
-                            }.get(part, pkg),
+                            "xc7k325tffg676":   "ffg676",
+                            "xc7k325tffg900":   "ffg900",
+                            "xc7k420tffg901":   "ffg901",
+                            }[part],
                        'speed' : speed
                }
    else:
        cst_type = "xdc"
-        # Artix/Spartan 7 Specific use case:
-        if family in ["Artix", "Spartan 7"]:
-            tool_options = {'part': f"{part}{pkg}-1"}
-        elif family == "Xilinx UltraScale":
+        if family == "Xilinx UltraScale":
            if part in ["xcvu9p-flga2104", "xcku5p-ffvb676"]:
                tool_options = {'part': part + '-1-e'}
                parameters["secondaryflash"]= {
@ -201,50 +161,32 @@ if tool in ["ise", "vivado"]:
                tool_options = {'part': part + '-2-e'}
            elif part == "xcvu37p-fsvh2892":
                tool_options = {'part': part + '-2L-e'}
-            elif part in ["xcku040-ffva1156", "xcku060-ffva1156"]:
-                tool_options = {'part': part + '-2-e'}
-                parameters["secondaryflash"]= {
-                    'datatype': 'int',
-                    'paramtype': 'vlogdefine',
-                    'description': 'secondary flash',
-                    'default': 1}
-            elif part == "xcau15p-ffvb676":
-                tool_options = {'part': part + '-2-e'}
        else:
            tool_options = {'part': part + '-1'}
-
    cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()
    files.append({'name': currDir + 'xilinx_spiOverJtag.v',
                  'file_type': 'verilogSource'})
    files.append({'name': cst_file, 'file_type': cst_type})
 else:
    full_part = {
-        "10cl016484" : "10CL016YU484C8G",
-        "10cl025256" : "10CL025YU256C8G",
-        "10cl055484" : "10CL055YU484C8G",
-        "ep4cgx15027": "EP4CGX150DF27I7",
-        "ep4ce11523" : "EP4CE115F23C7",
-        "ep4ce2217"  : "EP4CE22F17C6",
-        "ep4ce1523"  : "EP4CE15F23C8",
-        "ep4ce1017"  : "EP4CE10F17C8",
-        "ep4ce622"   : "EP4CE6E22C8",
-        "5ce215"     : "5CEBA2U15C8",
-        "5ce223"     : "5CEFA2F23I7",
-        "5ce523"     : "5CEFA5F23I7",
-        "5ce423"     : "5CEBA4F23C8",
-        "5ce927"     : "5CEBA9F27C7",
-        "5cse423"    : "5CSEMA4U23C6",
-        "5cse623"    : "5CSEBA6U23I7",
-        "5sgsd5"     : "5SGSMD5K2F40I3"}[part]
+        "10cl016484": "10CL016YU484C8G",
+        "10cl025256": "10CL025YU256C8G",
+        "10cl055484": "10CL055YU484C8G",
+        "ep4ce11523": "EP4CE115F23C7",
+        "ep4ce2217" : "EP4CE22F17C6",
+        "ep4ce1523" : "EP4CE15F23C8",
+        "5ce223"    : "5CEFA2F23I7",
+        "5ce523"    : "5CEFA5F23I7",
+        "5ce423"    : "5CEBA4F23C8",
+        "5ce927"    : "5CEBA9F27C7",
+        "5cse423"   : "5CSEMA4U23C6",
+        "5cse623"   : "5CSEBA6U23I7"}[part]
    files.append({'name': currDir + 'altera_spiOverJtag.v',
                  'file_type': 'verilogSource'})
    files.append({'name': currDir + 'altera_spiOverJtag.sdc',
                  'file_type': 'SDC'})
    tool_options = {'device': full_part, 'family':family}

-files.append({'name': currDir + 'spiOverJtag_core.v',
-              'file_type': 'verilogSource'})
-
 parameters[family.lower().replace(' ', '')]= {
    'datatype': 'int',
    'paramtype': 'vlogdefine',
@ -262,20 +204,7 @@ backend = get_edatool(tool)(edam=edam, work_root=build_dir)
 backend.configure()
 backend.build()

-if tool in ["vivado", "ise"]:
+if tool == "vivado":
    import shutil
-    import subprocess
-    import gzip
-
-    # Compress bitstream.
-    with open(f"tmp_{part}/spiOverJtag.bit", 'rb') as bit:
-        with gzip.open(f"spiOverJtag_{part}.bit.gz", 'wb', compresslevel=9) as bit_gz:
-            shutil.copyfileobj(bit, bit_gz)
-
-    # Create Symbolic links for all supported packages.
-    if family in ["Artix", "Spartan 7"]:
-        in_file = f"spiOverJtag_{part}.bit.gz"
-        for pkg in packages[family][part]:
-            out_file = f"spiOverJtag_{part}{pkg}.bit.gz"
-            if not os.path.exists(out_file):
-                subprocess.run(["ln", "-s", in_file, out_file])
+    shutil.copy("tmp_" + part + "/spiOverJtag.runs/impl_1/spiOverJtag.bit",
+            "tmp_" + part);
--- a/spiOverJtag/constr_xc6s_t_csg324.ucf
+++ b/spiOverJtag/constr_xc6s_t_csg324.ucf
@ -1,11 +0,0 @@
-CONFIG VCCAUX = "2.5";
-
-NET "sdi_dq0"  LOC = T13 | IOSTANDARD = LVCMOS25;
-NET "sdo_dq1"  LOC = R13 | IOSTANDARD = LVCMOS25;
-NET "wpn_dq2"  LOC = T14 | IOSTANDARD = LVCMOS25;
-NET "hldn_dq3" LOC = V14 | IOSTANDARD = LVCMOS25;
-NET "csn"      LOC = V3  | IOSTANDARD = LVCMOS25;
-NET "sck"      LOC = R15 | IOSTANDARD = LVCMOS25;
-
-NET "sck" TNM_NET = "PRDsck";
-TIMESPEC "TSsck" = PERIOD "PRDsck" 6 ns HIGH 50%;
--- a/spiOverJtag/constr_xc7a_cpg236.xdc
+++ b/spiOverJtag/constr_xc7a_cpg236.xdc
@ -2,12 +2,9 @@ set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
 set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports {csn}];
 set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
 set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
 set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
 set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];

-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_cpg238.xdc
+++ b/spiOverJtag/constr_xc7a_cpg238.xdc
@ -9,5 +9,3 @@ set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
 set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
 set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];

-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_csg324.xdc
+++ b/spiOverJtag/constr_xc7a_csg324.xdc
@ -8,6 +8,3 @@ set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
 set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
 set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
 set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_csg325.xdc
+++ b/spiOverJtag/constr_xc7a_csg325.xdc
@ -9,5 +9,3 @@ set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
 set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
 set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];

-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7a_csg325_1v35.xdc
+++ b/spiOverJtag/constr_xc7a_csg325_1v35.xdc
@ -1,24 +0,0 @@
-set_property CFGBVS GND [current_design]
-set_property CONFIG_VOLTAGE 1.8 [current_design]
-set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
-set_property CONFIG_MODE SPIx4 [current_design]
-set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
-set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
-set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
-
-set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
-set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
-set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
-
-set_property -dict {PACKAGE_PIN L15 IOSTANDARD SSTL135_R} [get_ports csn]
-set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL135_R} [get_ports sdi_dq0]
-set_property -dict {PACKAGE_PIN L17 IOSTANDARD SSTL135_R} [get_ports sdo_dq1]
-set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL135_R} [get_ports wpn_dq2]
-set_property -dict {PACKAGE_PIN J16 IOSTANDARD SSTL135_R} [get_ports hldn_dq3]
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7a_fbg484.xdc
+++ b/spiOverJtag/constr_xc7a_fbg484.xdc
@ -9,5 +9,3 @@ set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
 set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
 set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]

-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_fbg676.xdc
+++ b/spiOverJtag/constr_xc7a_fbg676.xdc
@ -1,13 +0,0 @@
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {csn}]
-set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
-set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
-set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
-set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_fgg484.xdc
+++ b/spiOverJtag/constr_xc7a_fgg484.xdc
@ -1,7 +1,6 @@
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

 set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
 set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
@ -9,5 +8,3 @@ set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
 set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
 set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]

-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_fgg676.xdc
+++ b/spiOverJtag/constr_xc7a_fgg676.xdc
@ -3,11 +3,9 @@ set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {csn}]
+set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
 set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
 set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
 set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
-set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]

-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_ftg256.xdc
+++ b/spiOverJtag/constr_xc7a_ftg256.xdc
@ -8,6 +8,3 @@ set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
 set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
 set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
 set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]
--- a/spiOverJtag/constr_xc7a_sbg384.xdc
+++ b/spiOverJtag/constr_xc7a_sbg384.xdc
@ -6,7 +6,4 @@ set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {csn}]
 set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]
 set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]
 set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]
-set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
+set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]
--- a/spiOverJtag/constr_xc7a_sbg484.xdc
+++ b/spiOverJtag/constr_xc7a_sbg484.xdc
@ -1,13 +0,0 @@
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
-set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
-set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
-set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
-set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
-set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7s_cpga196.xdc
+++ b/spiOverJtag/constr_xc7s_cpga196.xdc
@ -1,13 +0,0 @@
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
-set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS33} [get_ports {csn}];
-set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
-set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
-set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
-set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7s_csga225.xdc
+++ b/spiOverJtag/constr_xc7s_csga225.xdc
@ -8,6 +8,3 @@ set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
 set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
 set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
 set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7s_csga324.xdc
+++ b/spiOverJtag/constr_xc7s_csga324.xdc
@ -8,6 +8,3 @@ set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
 set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
 set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
 set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7s_fgga484.xdc
+++ b/spiOverJtag/constr_xc7s_fgga484.xdc
@ -1,13 +0,0 @@
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
-set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {csn}];
-set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
-set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
-set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
-set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7s_fgga676.xdc
+++ b/spiOverJtag/constr_xc7s_fgga676.xdc
@ -1,13 +0,0 @@
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
-set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {csn}];
-set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
-set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
-set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
-set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xc7s_ftgb196.xdc
+++ b/spiOverJtag/constr_xc7s_ftgb196.xdc
@ -1,13 +0,0 @@
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-
-set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {csn}];
-set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
-set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
-set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
-set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
-
-create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
-create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}
--- a/spiOverJtag/constr_xcau15p_ffvb676.xdc
+++ b/spiOverJtag/constr_xcau15p_ffvb676.xdc
@ -1,7 +0,0 @@
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-set_property CONFIG_VOLTAGE 1.8 [current_design]
-# Table 1-2 from UG570
-set_property CFGBVS GND [current_design]
-
-# Primary QSPI flash
-# Connection done through the STARTUPE3 block
--- a/spiOverJtag/constr_xcku040_ffva1156.xdc
+++ b/spiOverJtag/constr_xcku040_ffva1156.xdc
@ -1,25 +0,0 @@
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-set_property CONFIG_VOLTAGE 1.8 [current_design]
-# Table 1-5 from UG917
-set_property CFGBVS GND [current_design]
-
-# Primary QSPI flash
-# Connection done through the STARTUPE3 block
-# sdi_dq0  - PACKAGE_PIN AC7      - QSPI0_IO0                 Bank   0 - D00_MOSI_0
-# sdo_dq1  - PACKAGE_PIN AB7      - QSPI0_IO1                 Bank   0 - D01_DIN_0
-# wpn_dq2  - PACKAGE_PIN AA7      - QSPI0_IO2                 Bank   0 - D02_0
-# hldn_dq3 - PACKAGE_PIN Y7       - QSPI0_IO3                 Bank   0 - D03_0
-# csn      - PACKAGE_PIN U7       - QSPI0_CSB                 Bank   0 - RDWR_FCS_B_0
-# sck      - PACKAGE_PIN AA9      - FPGA_CCLK                 Bank   0 - CCLK_0
-
-# Secondary QSPI flash
-set_property PACKAGE_PIN M20       [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65
-set_property PACKAGE_PIN L20       [get_ports "sdo_sec_dq1"] ;# Bank  65 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_D05_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "sdo_sec_dq1"] ;# Bank  65 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_D05_65
-set_property PACKAGE_PIN R21       [get_ports "wpn_sec_dq2"] ;# Bank  65 VCCO - VCC1V8   - IO_L21P_T3L_N4_AD8P_D06_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "wpn_sec_dq2"] ;# Bank  65 VCCO - VCC1V8   - IO_L21P_T3L_N4_AD8P_D06_65
-set_property PACKAGE_PIN R22       [get_ports "hldn_sec_dq3"] ;# Bank  65 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_D07_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "hldn_sec_dq3"] ;# Bank  65 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_D07_65
-set_property PACKAGE_PIN G26       [get_ports "csn_sec"] ;# Bank  65 VCCO - VCC1V8   - IO_L2N_T0L_N3_FWE_FCS2_B_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "csn_sec"] ;# Bank  65 VCCO - VCC1V8   - IO_L2N_T0L_N3_FWE_FCS2_B_65
--- a/spiOverJtag/constr_xcku060_ffva1156.xdc
+++ b/spiOverJtag/constr_xcku060_ffva1156.xdc
@ -1,25 +0,0 @@
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-set_property CONFIG_VOLTAGE 1.8 [current_design]
-# Table 1-5 from UG917
-set_property CFGBVS GND [current_design]
-
-# Primary QSPI flash
-# Connection done through the STARTUPE3 block
-# sdi_dq0  - PACKAGE_PIN AC7      - QSPI0_IO0                 Bank   0 - D00_MOSI_0
-# sdo_dq1  - PACKAGE_PIN AB7      - QSPI0_IO1                 Bank   0 - D01_DIN_0
-# wpn_dq2  - PACKAGE_PIN AA7      - QSPI0_IO2                 Bank   0 - D02_0
-# hldn_dq3 - PACKAGE_PIN Y7       - QSPI0_IO3                 Bank   0 - D03_0
-# csn      - PACKAGE_PIN U7       - QSPI0_CSB                 Bank   0 - RDWR_FCS_B_0
-# sck      - PACKAGE_PIN AA9      - FPGA_CCLK                 Bank   0 - CCLK_0
-
-# Secondary QSPI flash
-set_property PACKAGE_PIN M20       [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65
-set_property PACKAGE_PIN L20       [get_ports "sdo_sec_dq1"] ;# Bank  65 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_D05_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "sdo_sec_dq1"] ;# Bank  65 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_D05_65
-set_property PACKAGE_PIN R21       [get_ports "wpn_sec_dq2"] ;# Bank  65 VCCO - VCC1V8   - IO_L21P_T3L_N4_AD8P_D06_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "wpn_sec_dq2"] ;# Bank  65 VCCO - VCC1V8   - IO_L21P_T3L_N4_AD8P_D06_65
-set_property PACKAGE_PIN R22       [get_ports "hldn_sec_dq3"] ;# Bank  65 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_D07_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "hldn_sec_dq3"] ;# Bank  65 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_D07_65
-set_property PACKAGE_PIN G26       [get_ports "csn_sec"] ;# Bank  65 VCCO - VCC1V8   - IO_L2N_T0L_N3_FWE_FCS2_B_65
-set_property IOSTANDARD  LVCMOS18  [get_ports "csn_sec"] ;# Bank  65 VCCO - VCC1V8   - IO_L2N_T0L_N3_FWE_FCS2_B_65
--- a/spiOverJtag/efinix_build.py
+++ b/spiOverJtag/efinix_build.py
@ -1,186 +0,0 @@
-#!/usr/bin/env python3
-
-import argparse
-import datetime
-import os
-import pathlib
-import pprint
-import re
-import sys
-
-from edalize.edatool import get_edatool
-from edalize.flows.efinity import Efinity
-
-#from xml.dom import expatbuilder
-#import xml.etree.ElementTree as et
-
-#efinity_home = os.environ["EFINITY_HOME"]
-#script_path  = efinity_home + "/scripts" 
-curr_path = os.getcwd()
-
-efinix_pinout = {
-    "Trion": {
-        "F49": { # t4/t8
-            "ss_n": "G3", "cclk": "F3", "cdi0": "F2", "cdi1": "F1", "cdi2": "E2", "cdi3": "D2",
-        },
-        "F81": { # t4/t8
-            "ss_n": "J4", "cclk": "H4", "cdi0": "F4", "cdi1": "H3", "cdi2": "J2", "cdi3": "F3",
-        },
-        "F169": { # t13/t20
-            "ss_n": "L1", "cclk": "K1", "cdi0": "J1", "cdi1": "J2", "cdi2": "F1", "cdi3": "G2",
-        },
-        "F256": { # t13/t20
-            "ss_n": "P3", "cclk": "H3", "cdi0": "L3", "cdi1": "N1", "cdi2": "K4", "cdi3": "L2",
-        },
-        "F324": { # t20/t85/t120
-            "ss_n": "P15", "cclk": "N13", "cdi0": "M13", "cdi1": "N14", "cdi2": "K14", "cdi3": "K18",
-        },
-        "F400": { # t20/
-            "ss_n": "W18", "cclk": "W19", "cdi0": "Y17", "cdi1": "Y18", "cdi2": "P15", "cdi3": "R17",
-        },
-        "Q100": { # t13/t20
-            "ss_n": "24", "cclk": "26", "cdi0": "19", "cdi1": "18", "cdi2": "8", "cdi3": "14",
-        },
-        "Q144": { # t20/
-            "ss_n": "31", "cclk": "30", "cdi0": "29", "cdi1": "28", "cdi2": "20", "cdi3": "19",
-        },
-        "W80": { # t20/
-            "ss_n": "K3", "cclk": "K2", "cdi0": "J1", "cdi1": "J2", "cdi2": "F1", "cdi3": "G2",
-        },
-    },
-    "Titanium": {
-        "J484": { # ti180, ...
-            "ss_n": "E2", "cclk": "J2", "cdi0": "G2", "cdi1": "H2", "cdi2": "F3", "cdi3": "G3",
-        },
-    },
-}
-
-timing_models = {
-    "T8F81": "C2",
-    "T13F256": "C3",
-    "TI180J484": "C3",
-}
-
-def gen_isf_constr(gateware_name, build_path, device_name, family, pkg):
-
-    # Basic settings
-    isf_array = [
-        "# Device setting",
-        "design.set_device_property(\"1A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
-        "design.set_device_property(\"1B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
-        "design.set_device_property(\"1C\",\"VOLTAGE\",\"1.1\",\"IOBANK\")",
-        "design.set_device_property(\"2A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
-        "design.set_device_property(\"2B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
-        "",
-    ]
-
-    # JTAG settings
-    isf_array.append("# ---------- JTAG 1 ---------")
-    isf_array.append("design.create_block(\"jtag_soc\", block_type=\"JTAG\")")
-    isf_array.append("design.assign_resource(\"jtag_soc\", \"JTAG_USER1\", \"JTAG\")")
-    jtag_pads = [
-        "CAPTURE", "DRCK", "RESET", "RUNTEST", "SEL", "SHIFT", "TCK", "TDI", "TMS", "UPDATE", "TDO"
-    ]
-
-    for pad in jtag_pads:
-        isf_array.append(f"design.set_property(\"jtag_soc\", \"{pad}\", \"jtag_1_{pad}\", \"JTAG\")")
-
-    # SPI pins settings
-    pins = efinix_pinout.get(family).get(pkg, None)
-    assert pins is not None
-    
-    pin_lst = [
-        {"name" : "csn",     "dir": "out", "pin": pins["ss_n"], "io_std": "3.3 V LVTTL / LVCMOS"},
-        {"name" : "sck",     "dir": "out", "pin": pins["cclk"], "io_std": "3.3 V LVTTL / LVCMOS"},
-        {"name" : "sdi_dq0", "dir": "out", "pin": pins["cdi0"], "io_std": "3.3 V LVTTL / LVCMOS"},
-        {"name" : "sdo_dq1", "dir": "in",  "pin": pins["cdi1"], "io_std": "3.3 V LVTTL / LVCMOS"},
-    ]
-    
-    for pin_cfg in pin_lst:
-        name = pin_cfg["name"]
-        pin_loc = pin_cfg["pin"]
-        if pin_cfg["dir"] == "in":
-            isf_array.append(f"design.create_input_gpio(\"{name}\")")
-        else:
-            isf_array.append(f"design.create_output_gpio(\"{name}\")")
-        isf_array.append(f"design.assign_pkg_pin(\"{name}\", \"{pin_loc}\")")
-    
-    isf_array.append("")
-
-    # Save ISF file
-    with open(os.path.join(build_dir, build_name+".isf"), "w") as fd:
-        fd.write("\n".join(isf_array))
-
-if __name__ == "__main__":
-    parser = argparse.ArgumentParser("SpiOverJtag for Efinix devices")
-    parser.add_argument("--device", help="Efinix Device")
-    args = parser.parse_args()
-
-    assert args.device is not None
-
-    device        = args.device.upper()
-    build_name    = "efinix_spiOverJtag"
-    build_dir     = os.path.join(curr_path, f"tmp_efinix_{device.lower()}")
-    timing_model  = timing_models.get(device, "C3")
-    sources       = [
-        {
-            'name': os.path.join(curr_path, "efinix_spiOverJtag.v"),
-            "file_type": "verilogSource",
-        },
-        {
-            'name': os.path.join(build_dir, "efinix_spiOverJtag.isf"),
-            "file_type": "ISF",
-        },
-    ]
-
-    force_restart = False
-
-    t = re.compile(r"(T[I]*)(\d+)(\w\d+)")
-    tt = t.match(device)
-    if tt is None:
-        print("fails")
-    else:
-        (fam, size, package) = tt.groups()
-        
-        assert fam in ["TI", "T"]
-
-        family = {True:"Titanium", False:"Trion"}[fam == "TI"]
-        if fam == "TI":
-            device = device.replace("TI", "Ti")
-
-        if os.path.exists(build_dir) and force_restart:
-            os.rmdir(build_dir)
-
-        if not os.path.exists(build_dir):
-            try:
-                os.mkdir(build_dir)
-            except FileExistsError:
-                pass
-
-        gen_isf_constr(
-            gateware_name = build_name,
-            build_path    = build_dir,
-            device_name   = device,
-            family        = family,
-            pkg           = package
-        )
-
-        tool_options = {
-            'part'   : device,
-            'family' : family,
-            'timing' : timing_model,
-        }
-
-        edam = {
-            'name'         : build_name,
-            'files'        : sources,
-            'flow_options' : tool_options,
-            'toplevel'     : 'spiOverJtag',
-        }
-        
-        backend = Efinity(edam=edam, work_root=build_dir)
-        backend.configure()
-        backend.build()
-
-        import shutil
-        shutil.copy(os.path.join(build_dir, "outflow", "efinix_spiOverJtag.bit"), build_dir)
--- a/spiOverJtag/spiOverJtag_5ce215.rbf.gz
+++ b/spiOverJtag/spiOverJtag_5ce215.rbf.gz
--- a/spiOverJtag/spiOverJtag_5sgsd5.rbf.gz
+++ b/spiOverJtag/spiOverJtag_5sgsd5.rbf.gz
--- a/spiOverJtag/spiOverJtag_core.v
+++ b/spiOverJtag/spiOverJtag_core.v
@ -1,250 +0,0 @@
-`default_nettype none
-/*
- * JTAG: rising edge: sampling
- *       falling esge: update
- * SPI:
- */
-
-module spiOverJtag_core (
-	/* JTAG state/controls */
-	input  wire sel,
-	input  wire capture,
-	input  wire update,
-	input  wire shift,
-	input  wire drck,
-	input  wire tdi,
-	output wire tdo,
-
-	/* JTAG endpoint to version */
-	input  wire ver_sel,
-	input  wire ver_cap,
-	input  wire ver_shift,
-	input  wire ver_drck,
-	input  wire ver_tdi,
-	output wire ver_tdo,
-	/* phys */
-	output reg  csn,
-	output wire sck,
-	output reg  sdi_dq0,
-	input  wire sdo_dq1,
-	output wire wpn_dq2,
-	output wire hldn_dq3,
-
-	/* debug signals */
-	output wire [ 6:0] dbg_header1,
-	output wire [13:0] dbg_header,
-	output wire [ 3:0] dbg_hdr_cnt,
-	output wire [ 2:0] dbg_jtag_state,
-	output wire        dbg_rst,
-	output wire        dbg_clk,
-	output wire        dbg_start_header,
-
-    output wire        dbg_ver_start,
-    output wire        dbg_ver_rst,
-    output wire        dbg_ver_state,
-    output wire [15:0] dbg_ver_cnt,
-    output wire [39:0] dbg_ver_shft
-);
-
-/* no global reset at start time:
- * reset system at capture time (before shift)
- * and at update time (after shift)
- */
-wire rst = ((capture | update) & sel);
-
-/*
- * if the FPGAs executing this code is somewhere in a complex
- * JTAG chain first bit isn't necessary for him
- * Fortunately dummy bits sent are equal to '0' -> we sent a 'start bit'
- */
-wire start_header = (tdi & shift & sel);
-
-localparam hdr_len = 16;
-reg  [hdr_len-1:0] header;     /* number of bits to receive / send in XFER state */
-reg  [hdr_len-1:0] header_d;
-/* Primary header with mode and length LSB
- * 6:5: mode (00: normal, 01: no header2, 10: infinite loop)
- * 4:0: Byte length LSB
- */
-reg  [        6:0] header1;
-reg  [        6:0] header1_d;
-wire [        6:0] header1_next = {tdi, header1[6:1]};
-wire [        1:0] mode         = header1[1:0];
-/* Secondary header with extended length */
-wire [hdr_len-1:0] header_next = {tdi, header[hdr_len-1:1]};
-reg  [        3:0] hdr_cnt; /* counter of bit received in RECV_HEADERx states */
-reg  [        3:0] hdr_cnt_d;
-
-/* ---------------- */
-/*       FSM        */
-/* ---------------- */
-
-localparam IDLE  = 3'b000,
-	RECV_HEADER1 = 3'b001,
-	RECV_HEADER2 = 3'b010,
-	XFER         = 3'b011,
-	WAIT_END     = 3'b100;
-
-reg [2:0] jtag_state, jtag_state_d;
-
-/*
- * 1. receives 8bits (
- */
-always @(*) begin
-	jtag_state_d = jtag_state;
-	hdr_cnt_d    = hdr_cnt;
-	header_d     = header;
-	header1_d    = header1;
-	case (jtag_state)
-		IDLE: begin /* nothing: wait for the 'start bit' */
-			hdr_cnt_d = 6;
-			if (start_header) begin
-				jtag_state_d = RECV_HEADER1;
-			end
-		end
-		RECV_HEADER1: begin /* first header with 1:0 : mode, 6:2: XFER length (LSB) */
-			hdr_cnt_d = hdr_cnt - 1'b1;
-			header1_d = header1_next;
-			if (hdr_cnt == 0) begin
-				if (header1_next[1:0] == 2'b00) begin
-					hdr_cnt_d    = 7;
-					header_d     = {header1_next[6:2], 3'b000, 8'd0};
-					jtag_state_d = RECV_HEADER2;
-				end else begin
-					header_d     = {8'b0, header1_next[6:2], 3'b000};
-					jtag_state_d = XFER;
-				end
-			end
-		end
-
-		RECV_HEADER2: begin /* fill a counter with 16bits (number of bits to pass to the flash) */
-			hdr_cnt_d = hdr_cnt - 1'b1;
-			header_d  = header_next;
-			if (hdr_cnt == 0) begin
-				jtag_state_d = XFER;
-			end
-		end
-		XFER: begin
-			header_d = header - 1;
-			if (header == 1 && mode != 2'b10)
-				jtag_state_d = WAIT_END;
-		end
-		WAIT_END: begin /* move to this state when header bits have been transfered to the SPI flash */
-		//	/* nothing to do: rst will move automagically state in IDLE */
-		end
-		default: begin
-			jtag_state_d = IDLE;
-		end
-	endcase
-end
-
-always @(posedge drck) begin
-	header  <= header_d;
-	header1 <= header1_d;
-	hdr_cnt <= hdr_cnt_d;
-end
-
-always @(posedge drck or posedge rst) begin
-	if (rst) begin
-		jtag_state <= IDLE;
-	end else begin
-		jtag_state <= jtag_state_d;
-	end
-end
-
-/* JTAG <-> phy SPI */
-always @(posedge drck or posedge rst) begin
-	if (rst) begin
-		sdi_dq0 <= 1'b0;
-		csn     <= 1'b1;
-	end else begin
-		sdi_dq0 <= tdi;
-		csn     <= ~(jtag_state == XFER);
-	end
-end
-
-assign sck      = ~drck;
-assign tdo      = sdo_dq1;
-assign wpn_dq2  = 1'b1;
-assign hldn_dq3 = 1'b1;
-
-/* ------------- */
-/*    Version    */
-/* ------------- */
-/* no global reset at start time: reset system at capture time (before shift) */
-wire ver_rst = (ver_cap & ver_sel);
-
-/* start bit */
-wire ver_start = (ver_tdi & ver_shift & ver_sel);
-
-localparam VER_VALUE = 40'h30_30_2E_32_30; // 02.00
-reg [ 6:0] ver_cnt, ver_cnt_d;
-reg [39:0] ver_shft, ver_shft_d;
-
-reg [2:0] ver_state, ver_state_d;
-always @(*) begin
-	ver_state_d = ver_state;
-	ver_cnt_d   = ver_cnt;
-    ver_shft_d  = ver_shft;
-	case (ver_state)
-		IDLE: begin /* nothing: wait for the 'start bit' */
-			ver_cnt_d = 6;
-			if (ver_start) begin
-				ver_state_d = RECV_HEADER1;
-			end
-		end
-		RECV_HEADER1: begin
-			ver_cnt_d = ver_cnt - 1'b1;
-			if (ver_cnt == 0) begin
-				ver_state_d = XFER;
-				ver_cnt_d   = 39;
-				ver_shft_d  = VER_VALUE;
-			end
-		end
-		XFER: begin
-			ver_cnt_d  = ver_cnt - 1;
-			ver_shft_d = {1'b1, ver_shft[39:1]};
-			if (ver_cnt == 0)
-				ver_state_d = WAIT_END;
-		end
-		WAIT_END: begin /* move to this state when header bits have been transfered to the SPI flash */
-		//  /* nothing to do: rst will move automagically state in IDLE */
-		end
-		default: begin
-			ver_state_d = IDLE;
-		end
-	endcase
-end
-
-always @(posedge ver_drck) begin
-	ver_cnt  <= ver_cnt_d;
-	ver_shft <= ver_shft_d;
-end
-
-always @(posedge ver_drck or posedge ver_rst) begin
-	if (ver_rst)
-		ver_state <= IDLE;
-	else
-		ver_state <= ver_state_d;
-end
-
-assign ver_tdo = ver_shft[0];
-
-/* --------- */
-/*   debug   */
-/* --------- */
-assign dbg_header1      = header1;
-assign dbg_header       = header;
-assign dbg_hdr_cnt      = hdr_cnt;
-assign dbg_jtag_state   = jtag_state;
-assign dbg_rst          = rst;
-assign dbg_clk          = ~drck;
-assign dbg_start_header = start_header;
-
-assign dbg_ver_start    = ver_start;
-assign dbg_ver_state    = ver_state;
-assign dbg_ver_cnt      = ver_cnt;
-assign dbg_ver_shft     = ver_shft;
-assign dbg_ver_rst      = ver_rst;
-
-endmodule
--- a/spiOverJtag/spiOverJtag_efinix_t13f256.bit.gz
+++ b/spiOverJtag/spiOverJtag_efinix_t13f256.bit.gz
--- a/spiOverJtag/spiOverJtag_efinix_ti180j484.bit.gz
+++ b/spiOverJtag/spiOverJtag_efinix_ti180j484.bit.gz
--- a/spiOverJtag/spiOverJtag_ep4ce1017.rbf.gz
+++ b/spiOverJtag/spiOverJtag_ep4ce1017.rbf.gz
--- a/spiOverJtag/spiOverJtag_ep4ce622.rbf.gz
+++ b/spiOverJtag/spiOverJtag_ep4ce622.rbf.gz
--- a/spiOverJtag/spiOverJtag_xc6slx25csg324.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc6slx25csg324.bit.gz
--- a/spiOverJtag/spiOverJtag_xc6slx25tcsg324.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc6slx25tcsg324.bit.gz
--- a/spiOverJtag/spiOverJtag_xc6slx45tfgg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc6slx45tfgg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a100t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a100t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a100tcsg324.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a100tcsg324.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a100tfgg484.bit
+++ b/spiOverJtag/spiOverJtag_xc7a100tfgg484.bit
--- a/spiOverJtag/spiOverJtag_xc7a100tfgg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a100tfgg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a100tfgg676.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a100tfgg676.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a100tftg256.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a100tftg256.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a12t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a12t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a12tcpg238.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a12tcpg238.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a12tcsg325.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a12tcsg325.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a15t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a15t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a15tcpg236.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a15tcpg236.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a15tcsg324.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a15tcsg324.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a15tcsg325.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a15tcsg325.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a15tfgg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a15tfgg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a15tftg256.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a15tftg256.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a200t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a200t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a200tfbg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a200tfbg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a200tfbg676.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a200tfbg676.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a200tffg1156.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a200tffg1156.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a200tsbg484.bit
+++ b/spiOverJtag/spiOverJtag_xc7a200tsbg484.bit
--- a/spiOverJtag/spiOverJtag_xc7a200tsbg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a200tsbg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a25t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a25t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a25tcpg238.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a25tcpg238.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a25tcsg325.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a25tcsg325.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a35t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a35t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a35tcpg236.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a35tcpg236.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a35tcsg324.bit
+++ b/spiOverJtag/spiOverJtag_xc7a35tcsg324.bit
--- a/spiOverJtag/spiOverJtag_xc7a35tcsg324.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a35tcsg324.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a35tcsg325.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a35tcsg325.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a35tfgg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a35tfgg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a35tftg256.bit
+++ b/spiOverJtag/spiOverJtag_xc7a35tftg256.bit
--- a/spiOverJtag/spiOverJtag_xc7a35tftg256.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a35tftg256.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a50t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a50t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a50tcpg236.bit
+++ b/spiOverJtag/spiOverJtag_xc7a50tcpg236.bit
--- a/spiOverJtag/spiOverJtag_xc7a50tcpg236.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a50tcpg236.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a50tcsg324.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a50tcsg324.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a50tcsg325.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a50tcsg325.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a50tcsg325_1v35.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a50tcsg325_1v35.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a50tfgg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a50tfgg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a50tftg256.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a50tftg256.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a75t.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a75t.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a75tcsg324.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a75tcsg324.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a75tfgg484.bit
+++ b/spiOverJtag/spiOverJtag_xc7a75tfgg484.bit
--- a/spiOverJtag/spiOverJtag_xc7a75tfgg484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a75tfgg484.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a75tfgg676.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a75tfgg676.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7a75tftg256.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7a75tftg256.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7k70tfbg676.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7k70tfbg676.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7s100.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7s100.bit.gz
--- a/spiOverJtag/spiOverJtag_xc7s100fgga484.bit.gz
+++ b/spiOverJtag/spiOverJtag_xc7s100fgga484.bit.gz
--- a/Show More
+++ b/Show More