f4cc1dad73
main: fix typo and check if manufacturer is supported
2019-12-27 14:00:30 +01:00
0b91d2dfbc
main: disable jtag verbose in all case
2019-12-20 07:57:32 +01:00
f0c066d716
introduce --list-cables, --list-boards and --list-fpga to display supported hardware
2019-12-07 06:40:29 +01:00
1ab5b9b4c1
fix part order family/model
2019-12-06 19:59:35 +01:00
873b073423
cycloader -> openFPGALoader
2019-12-06 11:51:47 +01:00
75c8fc0371
main: add gowin
2019-12-06 07:29:28 +01:00
d69efcfd08
main: add verbose parameter to xilinx and altera
2019-11-21 09:27:24 +01:00
04d6ad576d
main: use verbose, and transmit to cable and device
2019-11-21 08:39:27 +01:00
711833d034
main: delete jtag at the end
2019-11-19 09:03:09 +01:00
d739240280
main: add option to provides device path
2019-11-19 09:02:24 +01:00
d7a40fd5b0
main: add lattice support
2019-11-18 16:04:50 +01:00
53ad8dfda8
main: massive cleanup/rewrite
...
- since all about altera is hidden in a class suppress epcq, svf and
reset
- suppress everything about mode since each fpga dependant;
- some other cleanup
2019-09-28 15:46:12 +02:00
4530942e17
initial commit
2019-09-26 18:29:20 +02:00
Gwenhael Goavec-Merou