3ae5e5e4a5
xilinx: fixed spi/bpi select
2026-02-26 08:24:05 +01:00
35089045ea
latticeBitParser, lattice: added 128 clock pulses padding before preamble: Required by ECP3 family
2026-02-25 09:53:28 +01:00
0bc2594469
latticeBitParser: align configuration Data start address to the bitstream header offset
2026-02-25 09:51:33 +01:00
c4d26da89f
spiFlash: added Macronix MX25L6405
2026-02-23 08:33:47 +01:00
db7bd4770c
ch347jtag: align tms/tdi uses to others cables
2026-02-21 10:26:57 +01:00
a9af6cdd76
colognechip: 2x SLEEP_US because windows...
2026-02-18 19:42:34 +01:00
98fea26507
Adding BPI flash support and YPCB board support
2026-02-13 12:03:38 +01:00
c072042aa8
add arria 10 to part numbers list
2026-02-13 08:11:45 +01:00
63b0e34a6f
add maxII (EPM2210) to part numbers list
2026-02-12 17:29:06 +01:00
4d93073e99
handle other blaster PIDs
2026-02-12 17:25:44 +01:00
14086df9a2
altera: fixed done_bit_addr for 10M25SA, remains pgm_success_addr
2026-02-12 16:15:17 +01:00
fb61d309dc
part: added Altera 10M25S
2026-02-12 16:00:50 +01:00
99d59e45d4
ftdiJtagMPSSE: typo
2026-02-11 08:09:57 +01:00
68b4d7d654
ftdiJtagMPSSE: restructure SIPEED firmware test to uses strncomp only once with SIPEED keyword
2026-02-11 08:02:45 +01:00
d67d4ced64
Add workaround for slow JTAG on Sipeed Console
...
Signed-off-by: gatecat <gatecat@ds0.me>
2026-02-08 10:55:22 +01:00
e78b5e2995
CMakeLists.txt,main.cpp: option to enable/disable svf_jtag support
2026-01-29 16:16:40 +01:00
cc1dc3c868
CMakeLists.txt,main: added options to enable/disable vendors drivers
2026-01-29 16:06:17 +01:00
b3a8ea03d5
xilinx.cpp: nitpick
2026-01-29 14:43:35 +01:00
fb1768a175
xilinx: Fixed infinite loop in bit files smaller than 100
2026-01-28 22:13:05 +01:00
65ac4b24a3
Add xc7z007s
2026-01-21 20:50:19 -05:00
ecebc40004
Fix build with -DENABLE_FTDI_BASED_CABLE=off; fix potential array out-of-bounds access ( #616 )
...
* Fix build without FTDI cable
Signed-off-by: Qi Zhou <atmgnd@outlook.com>
* Fix potential array out‑of‑bounds access
Signed-off-by: Qi Zhou <atmgnd@outlook.com>
---------
Signed-off-by: Qi Zhou <atmgnd@outlook.com>
Co-authored-by: Qi Zhou <qi.zhou@unispc.com>
2026-01-21 14:38:30 +01:00
4767ec2ce2
src/part.hpp: Add missing Xilinx 7-series IDCODEs.
...
Add missing 7-series entries based on UG470 v1.17 Table 1-1.
Source:
- AMD UG470 (7 Series FPGAs Configuration User Guide), v1.17 (2023-12-05), Table 1-1
https://docs.amd.com/v/u/en-US/ug470_7Series_Config
2026-01-20 14:52:04 +01:00
87bf3c0f74
src/part.hpp: Add Xilinx Spartan UltraScale+ devices.
...
Extend fpga_list with Spartan UltraScale+ JTAG IDCODEs.
Source:
- https://docs.amd.com/r/en-US/ug860-spartan-configuration/Spartan-UltraScale-Devices-and-JTAG-IDCODEs
2026-01-20 14:40:04 +01:00
25ad02bb5e
src/part.hpp: Add missing Xilinx UltraScale+ device IDCODEs.
...
Extend fpga_list with additional UltraScale+ parts (Artix/Kintex/Virtex).
Source:
- https://review.openocd.org/c/openocd/+/7716
- https://sourceforge.net/p/openocd/mailman/openocd-devel/thread/20230525234809.B6A131B2%40openocd.org/
2026-01-20 14:15:02 +01:00
7432d49391
spiFlashdb: Added MX25V8035F NOR flash chip
2026-01-18 21:51:40 +01:00
a1599b63f8
Fix a small formatting error
...
`obuf - _obuf` returns `long` rather than `long long`
2026-01-07 15:51:17 -03:00
b870ee4c4f
jtag.cpp: ENABLE_ESP_USB_JTAG -> ENABLE_ESP_USB
2026-01-02 11:00:51 +01:00
0ce9fcb050
dirtyJtag: writeTDI: when end don't shift before applying last bit -> this Byte is correctly aligned during previous step
2026-01-02 10:04:02 +01:00
6a7bd29e0d
dirtyJtag: writeTDI: fixed last Byte align
2026-01-02 09:52:41 +01:00
d654a9d6d5
esp_usb_jtag: toggleClk: ignore tdi/tms and keep these pins to the current state
2026-01-01 12:46:39 +01:00
c7c0d94168
dirtyJtag: improves code / nitpick
2026-01-01 11:33:30 +01:00
097e236be8
dirtyJtag: writeTMS: honour tdi method parameter (required by gowin GW5A family)
2025-12-31 15:49:04 +01:00
936fe64c4a
ftdipp_mpsse.cpp: setClkFreq: flush buffers before changing clock frequency
2025-12-31 12:09:58 +01:00
2c6dac2d9c
lattice: fixed SRAM for NEXUS family
2025-12-30 15:50:19 +01:00
6f920360fc
lattice: fixed SPI Flash access for NEXUS Family
2025-12-30 11:34:35 +01:00
dd7b74d2f5
lattice: uses reg_content to defines status registers bits for Nexus family
2025-12-30 09:15:10 +01:00
c1c6e438a5
dirtyjtag: Allow custom VID/PID via command line options
...
Pass cable.vid and cable.pid to DirtyJtag constructor instead of using
hardcoded DIRTYJTAG_VID/PID. This allows users to use DirtyJTAG-compatible
firmware with custom USB VID/PID using the --vid and --pid flags:
openFPGALoader -c dirtyJtag --vid 0x1337 --pid 0x0001 bitstream.fs
This is useful for custom DirtyJTAG implementations, embedded microcontrollers
with built-in JTAG adapters, or devices that use MS OS 2.0 descriptors for
automatic WinUSB driver loading with different VID/PID.
The default VID/PID (0x1209:0xC0CA) is preserved for backward compatibility.
2025-12-27 16:12:31 +09:00
6bac72cd68
Global: added option to select/deselect all cables, added variables ENABLE_xxx to enable corresponding cables. Some vendor drivers needs to to be disabled accordlingly
2025-12-26 09:17:06 +01:00
84897ffa78
Enable support for CH347F
...
FIx a Windows issue
2025-12-24 12:13:56 -08:00
63a42344bc
lattice: rework program_extFlash method to uses new mcsParser features when extension == mcs
2025-12-17 20:05:11 +01:00
3706236b43
xilinx: rework program_spi method to uses new mcsParser features when extension == mcs
2025-12-17 20:05:11 +01:00
f349377f5f
mcsParser: reworks code to uses FlashDataSection
2025-12-17 20:05:11 +01:00
d7b9d58768
spiInterface: added write method variant with vector of FlashDataSection
2025-12-17 20:05:11 +01:00
f2c013daab
spiFlash: added erase_and_prog method with vector of FlashDataSection
2025-12-17 20:05:11 +01:00
4a593c258c
spiFlash: moved BP status, unlock step into a dedicatedmethod
2025-12-17 20:05:11 +01:00
a7e4303563
spiFlash: bulk_erase method: allows BP bypass and printXX with a verbose level
2025-12-17 20:05:11 +01:00
e302bb6edc
spiFlash: added FlashDataSection to handle bitstream per sections when gap or 0xff area are present
2025-12-17 20:05:11 +01:00
7ed4954c91
Merge pull request #599 from zh522130/fix-analogic-high-freq-flash
...
anlogic: fix high frequency flash programming issue
2025-12-13 08:55:14 +01:00
4c17327a65
anlogic: fix high frequency flash programming issue
2025-12-12 04:14:14 +00:00
ebf2f6fd80
efinix: Add header parsing and flash programming validation
...
Parse bitstream header to extract Mode, Width and Device fields.
Add validation for flash programming:
- Check device matches --fpga-part parameter
- Reject passive mode (only active mode supported for flash)
This prevents flashing incorrect bitstreams that would fail to boot.
2025-12-12 02:55:31 +00:00
206cbd68b7
src/gowin: Add support for GW5AT-15 (used on Sipeed Slogic16U3).
...
JTAG pinout on Sipeed Slogic16U3 is similar to Sipeed Tang Primier 20K JTAG pinout and
extension cable from Tang Primer 20K can be used.
./openFPGALoader -c digilent_hs2 --detect
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
index 0:
idcode 0x1681b
manufacturer Gowin
family GW5AT
model GW5AT-15
irlength 8
2025-12-10 10:57:18 +01:00
432cdc2dd7
lattice: added SPI Flash access support for ECP3 family
2025-12-08 16:24:40 +01:00
648a4a833a
basic PDI prog for Spartan Ultrascale+
2025-10-23 06:44:19 +02:00
617cd29dff
Update part.hpp to support Lattice LFE3-150EA device
...
This PR adds device ID support for the Lattice ECP3 LFE3-150EA.
Previously, only the LFE3-70E was supported.
We've tested the implementation and confirmed it works as expected.
We're happy to contribute to expanding ECP3 device support!
2025-10-02 11:32:19 +02:00
8694b3c295
board: added HyVision PCIe OPT01 rev.F (Kintex7 xc7k70tfbg676)
2025-09-24 16:56:46 +02:00
13cf0c59b9
xilinx: load_bridge: uses configBitstreamParser getFilename to print real name instead of theorical (with or without .gz)
2025-09-24 08:07:27 +02:00
6935936a92
configBitstreamParser: added filename getter
2025-09-24 08:06:28 +02:00
39b3ca5871
spiInterface: all methods: added a \n after command displayed (avoids unclear message when calee methods uses printxxx)
2025-09-24 08:06:06 +02:00
6df4bce1fd
xilinx: allows Flash write for Xilinx Spartan3 targets
2025-09-20 17:31:32 +02:00
e2c55f24c0
part: fixed cyclone III/IV/10 LP IDCODE (same code for all families)
2025-09-12 13:26:36 +02:00
c102426b78
Add altera EP4CE30 ( #584 )
2025-09-08 08:34:37 +02:00
cfddee3611
colognechip: add bulk erase + quad enable features and simplify spi_wait overload ( #582 )
...
* colognechip: add bulk erase + quad enable features and simplify spi_wait overload
* colognechip: remove unnecessary code in `set_quad_bit` and `bulk_erase_flash`
2025-09-03 16:26:16 +02:00
501d37e351
Merge pull request #581 from pu-cc/at25ql321
...
spiFlashdb: add AT25QL321
2025-09-03 14:38:11 +02:00
41e4a93f80
spiFlashdb: add AT25QL321
2025-09-03 14:11:28 +02:00
db64ec92cb
spiFlash: mask RDSR_WIP instead of RDSR_WEL while waiting for completion
2025-09-03 13:55:31 +02:00
bdcdea9a2f
cable: added altera usb blaster III variant
2025-08-27 18:26:17 +02:00
46a0560927
display: std::endl -> \n
2025-08-26 17:51:31 +02:00
850c3d74e0
progressBar: added eol for each progressBar update when no STDOUT_FILENO
2025-08-26 17:49:01 +02:00
2580aed994
esp_usb_jtag: added support for https://github.com/espressif/esp-usb-bridge + small adjusts
2025-08-25 09:38:00 +02:00
c818641cae
main: list_boards: print 'Undefined' when fpga_part or cable_name is empty
2025-08-07 11:00:49 +02:00
bc864100ff
main: list_boards now displays fpga_part too
2025-08-07 09:53:28 +02:00
c51c53ee33
Add Altera Cyclone 10 LP 10CL080
2025-07-28 13:27:06 +02:00
a53aedb137
gowin: added (undocumented) sequence to be performed when CRC Error bit is set
2025-07-20 10:23:19 +02:00
388f0b4c90
spiFlashdb: added XTX XT25F32B-S chip
2025-07-20 09:32:12 +02:00
b99672b69e
board: added ULX4M (DFU)
2025-07-19 09:45:04 +02:00
3b932dc542
colognechip: Simplify number of jtag bypass bits
2025-07-09 16:13:18 +02:00
3b1a40b798
part.hpp: MAX10: only keep size+Single(S)/Dual-supply(D). Sort between single-supply and dual-supply
2025-07-04 07:28:05 +02:00
4bd9840e46
altera: fix Wc99-designator
2025-07-02 07:17:17 +02:00
b2aa12b582
spiFlash, spiFlashdb: added global_lock flag and uses it instead of jedec_id ( #566 )
2025-06-30 18:26:22 +02:00
a1ea0c98fc
cmsisDAP: Avoid memcpy() on possibly overlapping buffer
...
I observed strange cmsisDAP behavior when building openFPGALoader with
Clang/musl in release mode: CmsisDAP:display_info() shows the correct
hardware capability that supports JTAG,
...
firmware version : 0254
hardware capabilities : 13
SWO trace buffer size : NA
...
but the detection of JTAG fails in the constructor with a strange
response sequence,
Hardware cap 00 01 00
JTAG init failed with: JTAG is not supported by the probe
With some digging, it's found that the CmsisDAP::xfer() method without
an instruction parameter may be called by the constructor with a rx_buff
pointer overlapping with _ll_buffer, for which memmove() instead of
memcpy() should be used. The behavior of memcpy() is undefined when dst
and src overlap.
Fixes: 53c5d35da6
2025-06-28 11:53:25 +00:00
e3e93a394e
main: SPI mode without board: check file_size (must be > 0)
2025-06-25 19:21:46 +02:00
dd3204a6e0
main, board: added --pins argument compatible with SPI mode
2025-06-25 19:10:13 +02:00
319c08e841
latticeSSPI: uses registers struct for status
2025-06-19 09:51:44 +02:00
dede406ebc
latticeSSPI: ECP5 driver for Slave SPI mode
2025-06-19 08:34:29 +02:00
21d4fccf28
altera,libusb_ll,mcsParser: fix some compiler's warnings
2025-06-19 08:30:35 +02:00
803bdfecce
altera: MAX10: added --flash-sector support with arbitrary binary file
2025-06-18 18:57:26 +02:00
775477ba8e
part: added Lattice ECP3 LFE3-70E
2025-06-18 16:20:32 +02:00
a7b56c3732
lattice: added ECP3 family support (SRAM only)
2025-06-18 16:20:23 +02:00
098cdd466a
jtag: allows caller to specify tdi level in toggleClk method
2025-06-18 10:01:16 +02:00
3723bf7571
Add cable support for ARM-USB-TINY-H based off ARM-USB-OCD-H
2025-06-10 21:54:54 +02:00
347088efb4
ice40: Reuses prepare_flash_access/post_flash_access as much as possible. Removed dupplicated Flash dump informations. Be coherent to status message
2025-06-08 07:20:00 +02:00
2e1c7e29a4
spiFlash: cosmetic 'Read flash ' -> 'Reading' ( #558 )
2025-06-08 07:01:14 +02:00
765ed526e3
spiFlash: dump: honour _verbose level
2025-06-04 21:38:00 +02:00
32f744979c
ice40: uses verbose_level for SPIFlash instead of verbose/quiet ( #555 )
2025-06-03 11:26:38 +02:00
c6d4a8bff1
device: added verbose_level attribute
2025-06-03 11:24:36 +02:00
5f6c1bfcd4
Merge pull request #543 from trabucayre/spiOverJtag_v2
...
SpiOverJtag v2
2025-05-29 08:41:10 +02:00
03045dc407
xilinx: adapted code to support existing spiOverJtag bitstreams (v1) and new bitstreams (v2)
2025-05-26 09:53:10 +02:00
ba48d53409
main: added detect_flash in SPI Mode and with a manufacturer
2025-05-24 07:50:51 +02:00
e135f1820b
ice40: added detect_flash support
2025-05-24 07:48:21 +02:00
10ba59c1ec
libusb_ll,ftdipp_mpsse: Bus and Device must be both == 0 to use filter or uses VID/PID
2025-05-24 07:46:58 +02:00
Gwenhael Goavec-Merou
blurbdust
Alberto Perro
gatecat
rkebelj
fisherdog4
atmgnd
Florent Kermarrec
Jernej Volk
letaldev
germaneguise
Patrick Dussud
zhangyh
Andrew E Wilson
hennomann
Andy
Patrick Urban
Denis Bodor
Yao Zi
José Miguel Sánchez García
Gwenhael Goavec-Merou