* fix(spiOverJtag): package-specific FGG676 bitstream build for QMTech XC7A100T
- Makefile: add xc7a100tfgg676 target
- build.py: parse device+package form (e.g. xc7a100tfgg676), stop aliasing
a package-specific bitstream to other packages via symlink
- constr_xc7a_fgg676.xdc: set BITSTREAM.STARTUP.STARTUPCLK JtagClk (camelCase;
all-caps JTAGCLK is silently rejected and falls back to Cclk, leaving EOS=0
over JTAG), correct SPI pins to LVCMOS33 per QMTech schematic
- README.md: document package-specific bitstream build
- remove stale spiOverJtag_xc7a100tfgg676.bit.gz (rebuilt by above)
* spiOverJtag: reword FGG676 SPI-flash pin comment as package-level
These pins are fixed by the XC7A*T-FGG676 package, not by the QMTech board.
Reword the comment to reflect that any XC7A35T/50T/75T/100T/200T in the FGG676
package routes the SPI-flash signals to the same balls. Keep the QMTech
schematic only as the cross-check reference. No pin values changed.
Addresses trabucayre review on constr_xc7a_fgg676.xdc.
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Co-authored-by: gHashTag <[email protected]>
Vasilev DmitriiandgHashTag
Gwenhael Goavec-Merou