Gwenhael Goavec-Merou
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5f9a8835da
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devices: simplify write RAM/Flash
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2021-02-18 21:09:34 +01:00 |
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Gwenhael Goavec-Merou
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ad21a3bb36
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recast verbose to int8_t to have more level of verbosity (-1 quiet, 0 normal, 1 verbose), add --quiet option, display progress bar when verbosity level >= 0
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2021-01-30 07:57:49 +01:00 |
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Gwenhael Goavec-Merou
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1992360667
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main: catch exception if FPGA can't be claimed.
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2021-01-29 06:19:42 +01:00 |
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Gwenhael Goavec-Merou
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6fefebd02c
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prepare release v0.2.1
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2020-12-17 13:58:30 +01:00 |
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Gwenhael Goavec-Merou
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14c5b8e681
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add support for ice40 FPGA and iCEBreaker, icestick, iCE40-HX8K, iCE40-HX1K-EVN boards
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2020-10-31 15:02:54 +01:00 |
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Gwenhael Goavec-Merou
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aa23aff388
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main: review SPI mode for efinix active mode
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2020-10-31 10:41:44 +01:00 |
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Gwenhael Goavec-Merou
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3c9870bba3
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introduce CBUS/DBUS pins value, add macro and pin mapping for board in SPI mode, reset and done signals
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2020-10-31 08:40:18 +01:00 |
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Gwenhael Goavec-Merou
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b2abafa76d
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ftdispi: start to use spi_pins_conf
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2020-10-30 08:26:15 +01:00 |
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Gwenhael Goavec-Merou
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5254116ad8
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main: if board has no default cable, don't override potential user choise
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2020-10-25 16:51:21 +01:00 |
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Gwenhael Goavec-Merou
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f22b25428d
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main: allow users board cable to be override
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2020-10-21 13:41:26 +02:00 |
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Gwenhael Goavec-Merou
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8fb36f9ba9
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main: improve flash direct access
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2020-10-07 07:47:46 +02:00 |
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Gwenhael Goavec-Merou
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522489c860
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main: improve previous commit
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2020-10-07 07:37:40 +02:00 |
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Gwenhael Goavec-Merou
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9e0614d15d
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main: fix ftdi_serial default value '' -> '-'. (jadafi)
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2020-10-07 06:39:00 +02:00 |
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Gwenhael Goavec-Merou
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f77faa2657
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add direct access to spi flash
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2020-10-06 08:38:24 +02:00 |
Martin Pittermann
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99929f99c3
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add ftdi serial argument
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2020-09-29 14:16:30 +02:00 |
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Gwenhael Goavec-Merou
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d9bbcdf68b
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xilinx: support writing .bit file to flash
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2020-09-25 18:58:31 +02:00 |
Rony Kelner
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41f1a7a61a
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review fixes: refactoring and readme update
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2020-09-22 19:22:51 +03:00 |
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Rony Kelner
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48c747edd6
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Add FTDI channel selection command line argument.
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2020-09-22 11:45:44 +03:00 |
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Gwenhael Goavec-Merou
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ad4dd39cdd
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main: pass write mode to anlogic constructor
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2020-08-24 08:55:27 +02:00 |
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Gwenhael Goavec-Merou
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e0d763c4b5
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add basic support for anlogic eagle s20 FPGA and lichee tang board
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2020-08-20 16:59:34 +02:00 |
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Gwenhael Goavec-Merou
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050aa94b8b
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main: delete jtag if someone is wrong
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2020-08-19 15:15:37 +02:00 |
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Gwenhael Goavec-Merou
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75f160ef00
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add CLI args to provide pin mapping for bitbang mode (ft232 and ft231x)
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2020-08-04 17:36:33 +02:00 |
Ed Bordin
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d24c63ec8a
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trabucayre/openFPGALoader#38 minor adjustments for MinGW build - use memset instead of bzero, errno_t may be replaced by int, provide ad-hoc ntohs on windows (alternative is link against winsock)
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2020-07-25 12:55:41 +10:00 |
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Gwenhael Goavec-Merou
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9c42aecef5
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replace argp by cxxopts
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2020-07-23 18:32:18 +02:00 |
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Gwenhael Goavec-Merou
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c1741b4300
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prepare release 0.1
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2020-07-11 08:47:54 +02:00 |
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Gwenhael Goavec-Merou
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d85fc68add
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main: use printError instead of cerr
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2020-07-11 07:47:27 +02:00 |
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Gwenhael Goavec-Merou
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447e3e47b2
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catch exception when claiming cable
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2020-07-11 07:23:24 +02:00 |
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Martin Pittermann
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e93034db69
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clean up --freq parser
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2020-05-25 10:33:09 +02:00 |
Martin Pittermann
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92888956f3
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add jtag frequency option
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2020-05-21 13:07:20 +02:00 |
Fabien Marteau
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6ec380516c
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tab or space indentation, please choose
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2020-04-22 20:51:54 +02:00 |
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Gwenhael Goavec-Merou
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12d69735eb
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main: pass wr sram/mem to lattice constructor and update help
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2020-04-22 15:23:38 +02:00 |
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Gwenhael Goavec-Merou
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8f2d6cb1c9
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add option to enable/disable udev support
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2020-03-14 19:42:07 +01:00 |
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Gwenhael Goavec-Merou
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c4f6178733
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propagate jtag_pins_conf_t and add support for bitbang mode
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2020-03-07 11:44:17 +01:00 |
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Gwenhael Goavec-Merou
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84298839ea
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rework board structure to add an optional pin mapping for bitbang mode
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2020-03-07 11:00:29 +01:00 |
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Gwenhael Goavec-Merou
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706219016e
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pass cable_t instead of mpsse_bit_config
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2020-03-07 10:56:34 +01:00 |
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Gwenhael Goavec-Merou
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1ef72b0da6
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add interface id in mpsse_bit_config.
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2020-03-07 07:19:20 +01:00 |
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Gwenhael Goavec-Merou
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9c9348f7d0
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rename ftdijtag to jtag
- drop everything about ftdi
- use jtagInterface to communicate with hardware
- for all class using jtag: rename FtdiJtag -> Jtag
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2020-03-06 09:05:57 +01:00 |
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Gwenhael Goavec-Merou
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d5e696b5c3
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add --detect option to display wich FPGA
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2020-02-22 20:55:51 +01:00 |
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Gwenhael Goavec-Merou
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849e5751e0
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main: catch exception, to finish cleanly
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2020-02-16 16:55:37 +01:00 |
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Gwenhael Goavec-Merou
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ad50f1a19b
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main: calls program() only when a bit_file is provided
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2020-02-16 16:53:55 +01:00 |
japm48
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2b2806b0b4
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Print error when no bitfile is specified
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2020-02-16 15:44:28 +01:00 |
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Gwenhael Goavec-Merou
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0315b3243c
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main: allows to have board without default cable
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2020-02-01 18:07:42 +01:00 |
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Fabien Marteau
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a86eff6b57
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Update cmake according to trabucayre request https://github.com/trabucayre/openFPGALoader/pull/17
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2020-01-27 09:47:42 +01:00 |