5f78204f22
Merge pull request #130 from abacomartin/master
...
adding support for MachXO3D
2021-11-20 15:35:01 +01:00
8df01663ff
main: raise error when board name is provided but not found
2021-11-11 17:20:51 +01:00
b6979f54f7
adding support for MachXO3D
2021-11-09 08:54:09 +00:00
649554f3fd
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
2021-10-23 08:44:23 +02:00
b1b1e5a4a8
main: don't limit vid/pid to dfu
2021-10-13 06:51:22 +02:00
6858cabc7d
main: introduce vid/pid args
2021-10-03 18:33:55 +02:00
ea613fa97a
dfu/main: add args to select altsetting and add filter to select corresponding interface
2021-10-03 12:39:06 +02:00
abef1f4968
add verbose-level args: -1 quiet, 0 normal mode, 1 verbose, 2 debug lowlevel
2021-10-03 08:22:35 +02:00
85b53b5918
add gowin external spi in bscan and --external-flash option
2021-09-15 20:18:49 +02:00
ae2fcfdca1
main: args. Fix comments for load and write bitstream
2021-09-13 14:10:42 +02:00
274d4ea2dc
main: fix display order for detect
2021-08-18 07:40:25 +02:00
630d4428c6
main: DFU mode: pass board vid/pid
2021-07-17 08:36:32 +02:00
be6ed217dd
main: display error message if program fails
2021-07-14 16:39:14 +02:00
cc688d6db6
main: small fix
2021-07-14 08:07:51 +02:00
13af012163
main: avoid potential miss with probe clock frequency
2021-07-14 08:04:43 +02:00
f8831f329c
Only use board clock speed if user does not specify an alternate freq
2021-07-11 15:27:46 +01:00
797785ce93
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
2021-07-11 15:20:15 +01:00
3983726a66
all devices: use spiFlash dump & verify
2021-07-11 11:34:14 +02:00
c99f5aa4e6
main: update to pass device type and prog type to altera class
2021-07-08 20:54:12 +02:00
8f95303daf
move to APACHE-2.0 license
2021-06-26 15:24:07 +02:00
98a2e836fa
ice40: add support for verify and dump
2021-06-26 08:43:02 +02:00
79a0e84f1f
efinix: add support for verify and dump
2021-06-26 08:34:12 +02:00
2af64e9af4
all: propagate verify with a message when not supported
2021-06-25 08:58:45 +02:00
fe0a315456
lattice,device: introduce method to dump flash content
2021-06-24 18:20:34 +02:00
c471d25bb5
xilinx,lattice,device: add verify write into flash
2021-06-24 18:08:02 +02:00
827767b99f
add proof of concept / draft for DFU protocol. Add orangeCrab in DFU mode
2021-06-20 10:26:05 +02:00
2f38461826
main: fix default args.index_chain
2021-05-15 19:30:45 +02:00
27af85dc19
main: add option to specify device index
2021-05-15 15:26:09 +02:00
acf4ab270c
main: rework fpga detection to allows more than one device in a chain, but only FPGA is allowed
2021-05-15 15:08:27 +02:00
42b7279a4b
main: add optional probe-firmware
2021-05-13 16:07:40 +02:00
7039465353
rework xilinx fpga spiOverJtag to respect model/package
2021-04-19 21:17:08 +02:00
f33d30dbce
main: fix bitbang check: config pins must be the shift value
2021-03-21 18:51:13 +01:00
16932786db
all parser:
...
- _raw_data is now filled in configBitstreamParser
- source may be a file or a pipe
- displayHeader become a common method (configBitstreamParser)
- improve/rewrite some parser (efinixHexparser 1s -> 11ms)
2021-02-24 06:36:48 +01:00
df52d523bf
All devices: new CLI argument to bypass file type autodetection
2021-02-21 18:30:13 +01:00
5f9a8835da
devices: simplify write RAM/Flash
2021-02-18 21:09:34 +01:00
ad21a3bb36
recast verbose to int8_t to have more level of verbosity (-1 quiet, 0 normal, 1 verbose), add --quiet option, display progress bar when verbosity level >= 0
2021-01-30 07:57:49 +01:00
1992360667
main: catch exception if FPGA can't be claimed.
2021-01-29 06:19:42 +01:00
6fefebd02c
prepare release v0.2.1
2020-12-17 13:58:30 +01:00
14c5b8e681
add support for ice40 FPGA and iCEBreaker, icestick, iCE40-HX8K, iCE40-HX1K-EVN boards
2020-10-31 15:02:54 +01:00
aa23aff388
main: review SPI mode for efinix active mode
2020-10-31 10:41:44 +01:00
3c9870bba3
introduce CBUS/DBUS pins value, add macro and pin mapping for board in SPI mode, reset and done signals
2020-10-31 08:40:18 +01:00
b2abafa76d
ftdispi: start to use spi_pins_conf
2020-10-30 08:26:15 +01:00
5254116ad8
main: if board has no default cable, don't override potential user choise
2020-10-25 16:51:21 +01:00
f22b25428d
main: allow users board cable to be override
2020-10-21 13:41:26 +02:00
8fb36f9ba9
main: improve flash direct access
2020-10-07 07:47:46 +02:00
522489c860
main: improve previous commit
2020-10-07 07:37:40 +02:00
9e0614d15d
main: fix ftdi_serial default value '' -> '-'. (jadafi)
2020-10-07 06:39:00 +02:00
f77faa2657
add direct access to spi flash
2020-10-06 08:38:24 +02:00
99929f99c3
add ftdi serial argument
2020-09-29 14:16:30 +02:00
d9bbcdf68b
xilinx: support writing .bit file to flash
2020-09-25 18:58:31 +02:00
Gwenhael Goavec-Merou
Martin Beynon
ultraembedded
Martin Pittermann