6a7bd29e0d
dirtyJtag: writeTDI: fixed last Byte align
2026-01-02 09:52:41 +01:00
d654a9d6d5
esp_usb_jtag: toggleClk: ignore tdi/tms and keep these pins to the current state
2026-01-01 12:46:39 +01:00
c7c0d94168
dirtyJtag: improves code / nitpick
2026-01-01 11:33:30 +01:00
097e236be8
dirtyJtag: writeTMS: honour tdi method parameter (required by gowin GW5A family)
2025-12-31 15:49:04 +01:00
936fe64c4a
ftdipp_mpsse.cpp: setClkFreq: flush buffers before changing clock frequency
2025-12-31 12:09:58 +01:00
2c6dac2d9c
lattice: fixed SRAM for NEXUS family
2025-12-30 15:50:19 +01:00
6f920360fc
lattice: fixed SPI Flash access for NEXUS Family
2025-12-30 11:34:35 +01:00
dd7b74d2f5
lattice: uses reg_content to defines status registers bits for Nexus family
2025-12-30 09:15:10 +01:00
c1c6e438a5
dirtyjtag: Allow custom VID/PID via command line options
...
Pass cable.vid and cable.pid to DirtyJtag constructor instead of using
hardcoded DIRTYJTAG_VID/PID. This allows users to use DirtyJTAG-compatible
firmware with custom USB VID/PID using the --vid and --pid flags:
openFPGALoader -c dirtyJtag --vid 0x1337 --pid 0x0001 bitstream.fs
This is useful for custom DirtyJTAG implementations, embedded microcontrollers
with built-in JTAG adapters, or devices that use MS OS 2.0 descriptors for
automatic WinUSB driver loading with different VID/PID.
The default VID/PID (0x1209:0xC0CA) is preserved for backward compatibility.
2025-12-27 16:12:31 +09:00
6bac72cd68
Global: added option to select/deselect all cables, added variables ENABLE_xxx to enable corresponding cables. Some vendor drivers needs to to be disabled accordlingly
2025-12-26 09:17:06 +01:00
84897ffa78
Enable support for CH347F
...
FIx a Windows issue
2025-12-24 12:13:56 -08:00
63a42344bc
lattice: rework program_extFlash method to uses new mcsParser features when extension == mcs
2025-12-17 20:05:11 +01:00
3706236b43
xilinx: rework program_spi method to uses new mcsParser features when extension == mcs
2025-12-17 20:05:11 +01:00
f349377f5f
mcsParser: reworks code to uses FlashDataSection
2025-12-17 20:05:11 +01:00
d7b9d58768
spiInterface: added write method variant with vector of FlashDataSection
2025-12-17 20:05:11 +01:00
f2c013daab
spiFlash: added erase_and_prog method with vector of FlashDataSection
2025-12-17 20:05:11 +01:00
4a593c258c
spiFlash: moved BP status, unlock step into a dedicatedmethod
2025-12-17 20:05:11 +01:00
a7e4303563
spiFlash: bulk_erase method: allows BP bypass and printXX with a verbose level
2025-12-17 20:05:11 +01:00
e302bb6edc
spiFlash: added FlashDataSection to handle bitstream per sections when gap or 0xff area are present
2025-12-17 20:05:11 +01:00
7ed4954c91
Merge pull request #599 from zh522130/fix-analogic-high-freq-flash
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anlogic: fix high frequency flash programming issue
2025-12-13 08:55:14 +01:00
4c17327a65
anlogic: fix high frequency flash programming issue
2025-12-12 04:14:14 +00:00
ebf2f6fd80
efinix: Add header parsing and flash programming validation
...
Parse bitstream header to extract Mode, Width and Device fields.
Add validation for flash programming:
- Check device matches --fpga-part parameter
- Reject passive mode (only active mode supported for flash)
This prevents flashing incorrect bitstreams that would fail to boot.
2025-12-12 02:55:31 +00:00
206cbd68b7
src/gowin: Add support for GW5AT-15 (used on Sipeed Slogic16U3).
...
JTAG pinout on Sipeed Slogic16U3 is similar to Sipeed Tang Primier 20K JTAG pinout and
extension cable from Tang Primer 20K can be used.
./openFPGALoader -c digilent_hs2 --detect
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
index 0:
idcode 0x1681b
manufacturer Gowin
family GW5AT
model GW5AT-15
irlength 8
2025-12-10 10:57:18 +01:00
432cdc2dd7
lattice: added SPI Flash access support for ECP3 family
2025-12-08 16:24:40 +01:00
648a4a833a
basic PDI prog for Spartan Ultrascale+
2025-10-23 06:44:19 +02:00
617cd29dff
Update part.hpp to support Lattice LFE3-150EA device
...
This PR adds device ID support for the Lattice ECP3 LFE3-150EA.
Previously, only the LFE3-70E was supported.
We've tested the implementation and confirmed it works as expected.
We're happy to contribute to expanding ECP3 device support!
2025-10-02 11:32:19 +02:00
8694b3c295
board: added HyVision PCIe OPT01 rev.F (Kintex7 xc7k70tfbg676)
2025-09-24 16:56:46 +02:00
13cf0c59b9
xilinx: load_bridge: uses configBitstreamParser getFilename to print real name instead of theorical (with or without .gz)
2025-09-24 08:07:27 +02:00
6935936a92
configBitstreamParser: added filename getter
2025-09-24 08:06:28 +02:00
39b3ca5871
spiInterface: all methods: added a \n after command displayed (avoids unclear message when calee methods uses printxxx)
2025-09-24 08:06:06 +02:00
6df4bce1fd
xilinx: allows Flash write for Xilinx Spartan3 targets
2025-09-20 17:31:32 +02:00
e2c55f24c0
part: fixed cyclone III/IV/10 LP IDCODE (same code for all families)
2025-09-12 13:26:36 +02:00
c102426b78
Add altera EP4CE30 ( #584 )
2025-09-08 08:34:37 +02:00
cfddee3611
colognechip: add bulk erase + quad enable features and simplify spi_wait overload ( #582 )
...
* colognechip: add bulk erase + quad enable features and simplify spi_wait overload
* colognechip: remove unnecessary code in `set_quad_bit` and `bulk_erase_flash`
2025-09-03 16:26:16 +02:00
501d37e351
Merge pull request #581 from pu-cc/at25ql321
...
spiFlashdb: add AT25QL321
2025-09-03 14:38:11 +02:00
41e4a93f80
spiFlashdb: add AT25QL321
2025-09-03 14:11:28 +02:00
db64ec92cb
spiFlash: mask RDSR_WIP instead of RDSR_WEL while waiting for completion
2025-09-03 13:55:31 +02:00
bdcdea9a2f
cable: added altera usb blaster III variant
2025-08-27 18:26:17 +02:00
46a0560927
display: std::endl -> \n
2025-08-26 17:51:31 +02:00
850c3d74e0
progressBar: added eol for each progressBar update when no STDOUT_FILENO
2025-08-26 17:49:01 +02:00
2580aed994
esp_usb_jtag: added support for https://github.com/espressif/esp-usb-bridge + small adjusts
2025-08-25 09:38:00 +02:00
c818641cae
main: list_boards: print 'Undefined' when fpga_part or cable_name is empty
2025-08-07 11:00:49 +02:00
bc864100ff
main: list_boards now displays fpga_part too
2025-08-07 09:53:28 +02:00
c51c53ee33
Add Altera Cyclone 10 LP 10CL080
2025-07-28 13:27:06 +02:00
a53aedb137
gowin: added (undocumented) sequence to be performed when CRC Error bit is set
2025-07-20 10:23:19 +02:00
388f0b4c90
spiFlashdb: added XTX XT25F32B-S chip
2025-07-20 09:32:12 +02:00
b99672b69e
board: added ULX4M (DFU)
2025-07-19 09:45:04 +02:00
3b932dc542
colognechip: Simplify number of jtag bypass bits
2025-07-09 16:13:18 +02:00
3b1a40b798
part.hpp: MAX10: only keep size+Single(S)/Dual-supply(D). Sort between single-supply and dual-supply
2025-07-04 07:28:05 +02:00
4bd9840e46
altera: fix Wc99-designator
2025-07-02 07:17:17 +02:00
Gwenhael Goavec-Merou
germaneguise
Patrick Dussud
zhangyh
Florent Kermarrec
Andrew E Wilson
hennomann
Andy
Patrick Urban
Denis Bodor