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openFPGALoader
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1638 Commits

Author SHA1 Message Date
Jean THOMAS 600b05a3c3
Fix typos 2021-08-07 23:22:30 +02:00
Jean THOMAS a1b890553c
Fix typo in INSTALL.md 
Co-authored-by: Hubert Hirtz <51088794+hhirtz@users.noreply.github.com>
 2021-08-03 22:03:56 +02:00
Jean THOMAS 5da3f7aa48 Rework project documentation 2021-08-03 21:02:36 +02:00
Gwenhael Goavec-Merou 3ea05cc1c6 prepare v0.5.0 2021-08-02 08:28:27 +02:00
Gwenhael Goavec-Merou 71d7f28ef7 README: better board and FPGA list 2021-08-02 08:28:14 +02:00
Gwenhael Goavec-Merou 84e85d4ebb
Merge pull request #101 from umarcor/ci/nightly 
ci: use eine/tip to release artifacts
 2021-07-21 07:03:23 +02:00
umarcor 07570f003e ci: use eine/tip to release artifacts 2021-07-17 20:11:02 +02:00
Gwenhael Goavec-Merou 0efe8313f3
Merge pull request #100 from umarcor/ci/ubuntu 
ci: add Ubuntu jobs
 2021-07-17 19:05:00 +02:00
umarcor 2d174a247b ci: add Ubuntu jobs 2021-07-17 18:38:52 +02:00
Gwenhael Goavec-Merou ef52dc3842
Merge pull request #65 from umarcor/ci/msys2 
CI: Windows/MSYS2 packaging
 2021-07-17 17:26:37 +02:00
umarcor ab53a4ac7f ci: test --detect (allow it to fail) 2021-07-17 17:03:23 +02:00
umarcor 21241cab37 msys2: fix license, now 'Apache-2.0' 2021-07-17 17:01:51 +02:00
umarcor b5b5005535 readme: add CI shield/badge 2021-07-17 16:20:57 +02:00
umarcor dddd8a92c8 create subdir 'scripts', mv msys2 there 2021-07-17 16:20:57 +02:00
Gwenhael Goavec-Merou 3585244b2b README: list all dependencies at the same place 2021-07-17 15:29:30 +02:00
umarcor a493ed0c3b ci: update 
* Split build and test into two jobs.
* Use emojis/icons.
* Build/test clang64 and ucrt64 too.
* Add workflow_dispatch.
 2021-07-17 12:27:57 +02:00
umarcor 0cd6b66d62 msys2: use 'MSYS Makefiles' 2021-07-17 11:35:38 +02:00
umarcor 6f7a452870 ci/msys2: show package content 2021-07-17 11:35:38 +02:00
umarcor 28ef4e1551 msys2: use mingw32-make 2021-07-17 11:35:38 +02:00
umarcor 685cf5c410 ci: add GitHub Actions workflow 'test' 2021-07-17 11:35:38 +02:00
umarcor 45ea128f32 msys: add PKGBUILD 2021-07-17 11:35:38 +02:00
Gwenhael Goavec-Merou 630d4428c6 main: DFU mode: pass board vid/pid 2021-07-17 08:36:32 +02:00
Gwenhael Goavec-Merou cbe2bf5494 dfu: try to open dfu vid/pid, next board vid/pid. without vid/pid download is forbidden. Simplify detection in not enumerate mode. Display iProduct 2021-07-17 08:36:13 +02:00
Gwenhael Goavec-Merou b8e2939776 board: add vid/pid for DFU at board level 2021-07-17 08:34:44 +02:00
Gwenhael Goavec-Merou 7113f4b36b part: add Gowin GW1N-2 2021-07-16 07:42:34 +02:00
Gwenhael Goavec-Merou 651fdd8beb ftdixx: improve workaround for arty. Not required with a classic ft2232 2021-07-14 19:09:39 +02:00
Gwenhael Goavec-Merou cd64bce4f2 fix warning in Debug mode 2021-07-14 17:59:02 +02:00
Gwenhael Goavec-Merou be6ed217dd main: display error message if program fails 2021-07-14 16:39:14 +02:00
Gwenhael Goavec-Merou 1e0a06288d configBitstreamParser: don't compute reverseByte, use a precomputed table: gain: 200ms for arty @30MHz 2021-07-14 08:44:22 +02:00
Gwenhael Goavec-Merou cc688d6db6 main: small fix 2021-07-14 08:07:51 +02:00
Gwenhael Goavec-Merou 894cda820f board: add default frequency option for BITBANG and SPI boards 2021-07-14 08:05:36 +02:00
Gwenhael Goavec-Merou 13af012163 main: avoid potential miss with probe clock frequency 2021-07-14 08:04:43 +02:00
Gwenhael Goavec-Merou fd329158de
Merge pull request #98 from ultraembedded/master 
Add board specific default frequency
 2021-07-14 07:53:13 +02:00
Gwenhael Goavec-Merou acf7d2a0a8 ftdiJtagMPSSE: add work around to deal with freq >= 15MHz 2021-07-13 07:00:30 +02:00
Gwenhael Goavec-Merou 594f065116 ftdipp_mpsse: use runtime_error instead of simple exception 2021-07-12 08:05:25 +02:00
ultraembedded f8831f329c Only use board clock speed if user does not specify an alternate freq 2021-07-11 15:27:46 +01:00
ultraembedded 797785ce93 Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested). 2021-07-11 15:20:15 +01:00
Gwenhael Goavec-Merou 3983726a66 all devices: use spiFlash dump & verify 2021-07-11 11:34:14 +02:00
Gwenhael Goavec-Merou f5254294eb altera: add verify and dump 2021-07-11 11:32:35 +02:00
Gwenhael Goavec-Merou b77c5a22df spiFlash: add verify and dump method 2021-07-11 11:32:10 +02:00
Gwenhael Goavec-Merou f19d0996a4 progressBar: limit resolution 2021-07-11 11:30:02 +02:00
Gwenhael Goavec-Merou 6a1f67bc69 spiOverJtag: add constr_xc6s_csg324 2021-07-11 09:05:15 +02:00
Gwenhael Goavec-Merou 6639f0646a board: pipistrello: add spi flash support 2021-07-11 08:58:40 +02:00
Gwenhael Goavec-Merou 0d57b58c26 spiOverJtag: use build.py for all devices, add xc6slx45 2021-07-11 08:57:46 +02:00
Gwenhael Goavec-Merou 7d3000f88d spiOverJtag: rewrite xilinx spiOverJtag vhd -> v 2021-07-11 08:57:00 +02:00
Gwenhael Goavec-Merou 7137103db1 update README 2021-07-11 08:49:39 +02:00
Gwenhael Goavec-Merou c90a4b7734 altera: spi flash support for cycloneV and qmtech 2021-07-10 08:20:27 +02:00
Gwenhael Goavec-Merou 0c4aedcb23 altera: add spi flash support for de0nano (EP4CE22F17C6) 2021-07-09 07:40:55 +02:00
Gwenhael Goavec-Merou 592cbd87b7 spiOverJtag: add real bridge (virtual jtag) for cyc1000 and build system based on edalize 2021-07-08 20:59:28 +02:00
Gwenhael Goavec-Merou c99f5aa4e6 main: update to pass device type and prog type to altera class 2021-07-08 20:54:12 +02:00