8b021bdd3a
ftdijtag: add shiftIR variant with value passed by value instead of ref. Used when the command is up to 8bits with no read
2019-10-04 08:25:37 +02:00
53ad8dfda8
main: massive cleanup/rewrite
...
- since all about altera is hidden in a class suppress epcq, svf and
reset
- suppress everything about mode since each fpga dependant;
- some other cleanup
2019-09-28 15:46:12 +02:00
9b683825b3
ignore swp
2019-09-28 15:40:46 +02:00
04360e9b26
altera: fix spi bridge path
2019-09-28 15:40:21 +02:00
fd661c5e6f
ftdipp_mpsse: add method to access vid and pid
2019-09-28 15:38:57 +02:00
2f3fd12476
ftdipp_mpsse: add missing vid
2019-09-28 15:38:25 +02:00
f59ea6deba
ftdipp_mpsse: informations message must be displayed only on verbose mode
2019-09-28 15:37:51 +02:00
7a220bf4e4
ftdipp_mpsse: all error are now redirected on stderr
2019-09-28 15:37:10 +02:00
d8d974d871
svf_jtag: add ifndef ... endif in hpp file to avoid multiple definition
2019-09-28 15:34:44 +02:00
ecdde91dff
Altera:
...
- merge epcq and svf into the class
- merge reset()
- check in constructor file type to determine if bitstream is to send in
sram or spi flash
2019-09-28 15:31:43 +02:00
c5e26c0c69
Xilinx:
...
- adapt method signature to Device modifications
- suppress useless methods
- disable not working reset()
2019-09-28 15:27:58 +02:00
66fbbce59a
Device:
...
- suppress prog_mode to the constructor and set mode to NONE_MODE
- parse file extension
- program, idCode and reset are now virtual
2019-09-28 15:26:47 +02:00
52889506a5
README: improve CYC1000 section (svf and rpd conversion).
2019-09-27 08:58:38 +02:00
bf6bf3787d
ignore cycloader binary file
2019-09-26 18:53:58 +02:00
60d5ecbf74
complete README: install/help/usage
2019-09-26 18:53:30 +02:00
9a6469f2fa
add svf used to have access to SPI flash through FT2232 interface B
2019-09-26 18:39:03 +02:00
5294d26702
add missing Makefile
2019-09-26 18:38:37 +02:00
ba10ae8d40
update README
2019-09-26 18:30:36 +02:00
4530942e17
initial commit
2019-09-26 18:29:20 +02:00
62af4cd266
Initial commit
2019-09-26 18:27:33 +02:00
Gwenhael Goavec-Merou