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spiOverJtag: add support and bitstreams for xcku040 and xcku060

This commit is contained in:
bma 2024-09-22 13:02:37 +02:00 committed by Gwenhael Goavec-Merou
parent abb64a6aa1
commit f3a48fb3b1
6 changed files with 64 additions and 4 deletions
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1
spiOverJtag/Makefile
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@ -16,6 +16,7 @@ XILINX_PARTS := xc3s500evq100 \
xc7k420tffg901 \ xc7k420tffg901 \
xcku3p-ffva676 \ xcku3p-ffva676 \
xc7vx330tffg1157 \ xc7vx330tffg1157 \
xcku040-ffva1156 xcku060-ffva1156 \
xcku5p-ffvb676 \ xcku5p-ffvb676 \
xcvu9p-flga2104 xcvu37p-fsvh2892 xcvu9p-flga2104 xcvu37p-fsvh2892
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

17
spiOverJtag/build.py
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@ -93,7 +93,7 @@ if tool in ["ise", "vivado"]:
"xc7a35tfgg484" : "xc7a_fgg484", "xc7a35tfgg484" : "xc7a_fgg484",
"xc7a50tcpg236" : "xc7a_cpg236", "xc7a50tcpg236" : "xc7a_cpg236",
"xc7a50tcsg324" : "xc7a_csg324", "xc7a50tcsg324" : "xc7a_csg324",
"xc7a50tfgg484" : "xc7a_fgg484", "xc7a50tfgg484" : "xc7a_fgg484",
"xc7a75tfgg484" : "xc7a_fgg484", "xc7a75tfgg484" : "xc7a_fgg484",
"xc7a100tcsg324" : "xc7a_csg324", "xc7a100tcsg324" : "xc7a_csg324",
"xc7a100tfgg484" : "xc7a_fgg484", "xc7a100tfgg484" : "xc7a_fgg484",
@ -112,10 +112,12 @@ if tool in ["ise", "vivado"]:
"xc7s25csga225" : "xc7s_csga225", "xc7s25csga225" : "xc7s_csga225",
"xc7s25csga324" : "xc7s_csga324", "xc7s25csga324" : "xc7s_csga324",
"xc7s50csga324" : "xc7s_csga324", "xc7s50csga324" : "xc7s_csga324",
"xcvu9p-flga2104" : "xcvu9p_flga2104", "xcku040-ffva1156" : "xcku040_ffva1156",
"xcku060-ffva1156" : "xcku060_ffva1156",
"xcvu9p-flga2104" : "xcvu9p_flga2104",
"xcvu37p-fsvh2892" : "xcvu37p_fsvh2892", "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
"xcku3p-ffva676" : "xcku3p_ffva676", "xcku3p-ffva676" : "xcku3p_ffva676",
"xcku5p-ffvb676" : "xcku5p_ffvb676", "xcku5p-ffvb676" : "xcku5p_ffvb676",
}[part] }[part]
if tool == "ise": if tool == "ise":
cst_type = "UCF" cst_type = "UCF"
@ -172,6 +174,13 @@ if tool in ["ise", "vivado"]:
tool_options = {'part': part + '-2-e'} tool_options = {'part': part + '-2-e'}
elif part == "xcvu37p-fsvh2892": elif part == "xcvu37p-fsvh2892":
tool_options = {'part': part + '-2L-e'} tool_options = {'part': part + '-2L-e'}
elif part in ["xcku040-ffva1156", "xcku060-ffva1156"]:
tool_options = {'part': part + '-2-e'}
parameters["secondaryflash"]= {
'datatype': 'int',
'paramtype': 'vlogdefine',
'description': 'secondary flash',
'default': 1}
else: else:
tool_options = {'part': part + '-1'} tool_options = {'part': part + '-1'}
cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower() cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()

25
spiOverJtag/constr_xcku040_ffva1156.xdc Normal file
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@ -0,0 +1,25 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-5 from UG917
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AC7 - QSPI0_IO0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AB7 - QSPI0_IO1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AA7 - QSPI0_IO2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN Y7 - QSPI0_IO3 Bank 0 - D03_0
# csn - PACKAGE_PIN U7 - QSPI0_CSB Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN AA9 - FPGA_CCLK Bank 0 - CCLK_0
# Secondary QSPI flash
set_property PACKAGE_PIN M20 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN L20 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R21 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R22 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN G26 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65

25
spiOverJtag/constr_xcku060_ffva1156.xdc Normal file
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@ -0,0 +1,25 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-5 from UG917
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AC7 - QSPI0_IO0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AB7 - QSPI0_IO1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AA7 - QSPI0_IO2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN Y7 - QSPI0_IO3 Bank 0 - D03_0
# csn - PACKAGE_PIN U7 - QSPI0_CSB Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN AA9 - FPGA_CCLK Bank 0 - CCLK_0
# Secondary QSPI flash
set_property PACKAGE_PIN M20 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN L20 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R21 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R22 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN G26 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65

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spiOverJtag/spiOverJtag_xcku040-ffva1156.bit.gz Normal file
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spiOverJtag/spiOverJtag_xcku060-ffva1156.bit.gz Normal file
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