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Icenowy Zheng 2026-02-08 15:49:59 +01:00 committed by GitHub
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@ -282,6 +282,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
/* Altera Stratix V */
{0x029070dd, {"altera", "stratix V GS", "5SGSD5", 10}},
/* Altera Arria 10 */
{0x02e060dd, {"altera", "arria 10 GX", "10AX115", 10}},
/**************************************************************************/
/* Efinix */
/**************************************************************************/