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openFPGALoader
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Merge 2a59256872 into a266aafa1e

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Dave Keeshan 2026-07-14 16:52:25 +00:00 committed by GitHub
parent a266aafa1e 2a59256872
commit edc6542c24
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14
doc/boards.yml
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@ -34,6 +34,20 @@
Memory: OK
Flash: OK
- ID: alinx_axku042
Description: ALINX AXKU042 Kintex UltraScale FPGA Dev Board
URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Kintex-UltraScale/AXKU042.html
FPGA: Kintex UltraScale xcku040-ffva1156
Memory: OK
Flash: OK
- ID: alinx_axku062
Description: ALINX AXKU062 Kintex UltraScale FPGA Dev Board
URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Kintex-UltraScale/AXKU062.html
FPGA: Kintex UltraScale xcku060-ffva1156
Memory: OK
Flash: OK
- ID: alinx_axku095
Description: ALINX AXKU095 Kintex UltraScale FPGA Dev Board
URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Kintex-UltraScale/AXKU095.html

2
src/board.hpp
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@ -124,6 +124,8 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", SPI_FLASH, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7201", "xc7a200tfbg484", "", SPI_FLASH, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7203", "xc7a200tfbg484", "", SPI_FLASH, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_axku042", "xcku040-ffva1156", "digilent_hs2", SPI_FLASH, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_axku062", "xcku060-ffva1156", "digilent_hs2", SPI_FLASH, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_axku095", "xcku095-ffva1156", "digilent_hs2", SPI_FLASH, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", SPI_FLASH, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr5_tester", "xc7k160tffg676", "ft4232", SPI_FLASH, 0, 0, CABLE_DEFAULT),