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openFPGALoader
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As per feedback, allow 232H devices to have upper bank pins configured on init.

This commit is contained in:
ultraembedded 2021-06-11 11:24:57 +01:00
parent 291f1b6d6f
commit dc003f6212
3 changed files with 2 additions and 3 deletions
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2
src/cable.hpp
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@ -32,7 +32,7 @@ static std::map <std::string, cable_t> cable_list = {
{"digilent_b", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}},
{"digilent_ad", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x80, 0x80, true}}},
{"digilent_ad", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x80, 0x80}}},
{"dirtyJtag", {MODE_DIRTYJTAG, {}}},
{"efinix_spi", {MODE_FTDI_SERIAL, {0x0403, 0x6011, INTERFACE_A, 0x08, 0x8B, 0x00, 0x00}}},
{"ft2232", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}},

2
src/ftdipp_mpsse.cpp
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@ -186,7 +186,7 @@ int FTDIpp_MPSSE::init(unsigned char latency, unsigned char bitmask_mode,
buf_cmd[1] = _cable.bit_low_val; // 0xe8;
buf_cmd[2] = _cable.bit_low_dir; // 0xeb;
if (_cable.force_high_bits || (_ftdi->type != TYPE_4232H && _ftdi->type != TYPE_232H)) {
if (_ftdi->type != TYPE_4232H) {
buf_cmd[4] = _cable.bit_high_val; // 0x00;
buf_cmd[5] = _cable.bit_high_dir; // 0x60;
to_wr = 6;

1
src/ftdipp_mpsse.hpp
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@ -13,7 +13,6 @@ class FTDIpp_MPSSE {
int bit_low_dir;
int bit_high_val;
int bit_high_dir;
int force_high_bits;
} mpsse_bit_config;
FTDIpp_MPSSE(const mpsse_bit_config &cable, const std::string &dev,