latticeSSPI: new Driver to access Lattice ECP5 via Slave SPI
This commit is contained in:
Gwenhael Goavec-Merou
parent
765ed526e3
commit
dbc46cdaff
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@ -100,7 +100,6 @@ set(OPENFPGALOADER_SOURCE
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src/efinix.cpp
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src/efinixHexParser.cpp
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src/fx2_ll.cpp
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src/ice40.cpp
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src/ihexParser.cpp
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src/pofParser.cpp
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src/rawParser.cpp
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@ -109,8 +108,6 @@ set(OPENFPGALOADER_SOURCE
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src/usbBlaster.cpp
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src/epcq.cpp
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src/svf_jtag.cpp
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src/jedParser.cpp
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src/feaparser.cpp
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src/display.cpp
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src/jtag.cpp
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src/ftdiJtagBitbang.cpp
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@ -118,12 +115,10 @@ set(OPENFPGALOADER_SOURCE
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src/configBitstreamParser.cpp
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src/ftdipp_mpsse.cpp
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src/main.cpp
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src/latticeBitParser.cpp
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src/libusb_ll.cpp
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src/gowin.cpp
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src/device.cpp
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src/jlink.cpp
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src/lattice.cpp
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src/progressBar.cpp
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src/fsparser.cpp
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src/mcsParser.cpp
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@ -152,7 +147,6 @@ set(OPENFPGALOADER_HEADERS
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src/efinix.hpp
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src/efinixHexParser.hpp
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src/fx2_ll.hpp
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src/ice40.hpp
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src/ihexParser.hpp
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src/pofParser.hpp
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src/progressBar.hpp
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@ -168,8 +162,6 @@ set(OPENFPGALOADER_HEADERS
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src/fsparser.hpp
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src/part.hpp
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src/board.hpp
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src/jedParser.hpp
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src/feaparser.hpp
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src/display.hpp
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src/mcsParser.hpp
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src/ftdipp_mpsse.hpp
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@ -183,8 +175,6 @@ set(OPENFPGALOADER_HEADERS
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src/gowin.hpp
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src/cable.hpp
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src/ftdispi.hpp
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src/lattice.hpp
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src/latticeBitParser.hpp
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src/xilinx.hpp
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src/xilinxMapParser.hpp
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src/colognechip.hpp
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@ -192,6 +182,25 @@ set(OPENFPGALOADER_HEADERS
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src/esp_usb_jtag.hpp
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)
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# Lattice Drivers / Files parsers.
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list(APPEND OPENFPGALOADER_SOURCE
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src/ice40.cpp
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src/lattice.cpp
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src/latticeSSPI.cpp
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src/feaparser.cpp
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src/jedParser.cpp
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src/latticeBitParser.cpp
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)
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list(APPEND OPENFPGALOADER_HEADERS
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src/ice40.hpp
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src/lattice.hpp
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src/latticeSSPI.hpp
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src/jedParser.hpp
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src/feaparser.hpp
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src/latticeBitParser.hpp
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)
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link_directories(
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${LIBUSB_LIBRARY_DIRS}
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${LIBFTDI_LIBRARY_DIRS}
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@ -0,0 +1,374 @@
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// SPDX-License-Identifier: Apache-2.0
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/*
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* Copyright (C) 2025 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*/
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#define __STDC_FORMAT_MACROS
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#include <iostream>
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#include <string>
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#include <cinttypes>
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#include <string.h>
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#include <unistd.h>
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#include "device.hpp"
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#include "ftdispi.hpp"
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#include "latticeBitParser.hpp"
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#include "progressBar.hpp"
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#include "latticeSSPI.hpp"
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#define SSPI_READ_ID 0xE0
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#define SSPI_ISC_READ_STATUS 0x3C
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#define ISC_ENABLE 0xC6 /* ISC_ENABLE - Offline Mode */
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#define ISC_DISABLE 0x26 /* ISC_DISABLE */
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#define READ_BUSY_FLAG 0xF0
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#define FLASH_ERASE 0x0E
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# define REG_STATUS_DONE (1 << 8) /* Flash or SRAM Done Flag (ISC_EN=0 -> 1 Successful Flash to SRAM transfer, ISC_EN=1 -> 1 Programmed) */
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# define REG_STATUS_ISC_EN (1 << 9) /* Enable Configuration Interface (1=Enable, 0=Disable) */
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# define REG_STATUS_BUSY (1 << 12) /* Busy Flag (1 = Busy) */
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# define REG_STATUS_FAIL (1 << 13) /* Fail Flag (1 = Operation failed) */
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# define REG_STATUS_PP_CFG (1 << 15) /* Password Protection All Enabled for CFG0 and CFG1 flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_PP_FSK (1 << 16) /* Password Protection Enabled for Feature and Security Key flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_PP_UFM (1 << 17) /* Password Protection enabled for all UFM flash sectors 0=Disabled (Default), 1=Enabled */
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# define REG_STATUS_AUTH_DONE (1 << 18) /* Authentication done */
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# define REG_STATUS_PRI_BOOT_FAIL (1 << 21) /* Primary boot failure (1= Fail) even though secondary boot successful */
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# define REG_STATUS_CNF_CHK_MASK (0x0f << 23) /* Configuration Status Check */
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# define REG_STATUS_EXEC_ERR (1 << 26) /*** NOT specified for MachXO3D ***/
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# define REG_STATUS_DEV_VERIFIED (1 << 27) /* I=0 Device verified correct, I=1 Device failed to verify */
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LatticeSSPI::LatticeSSPI(FtdiSpi *spi, const std::string &filename,
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const std::string &file_type,
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const int8_t verbose):
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Device(NULL, filename, file_type, false, verbose), _spi(spi)
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{
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_spi->setMode(0);
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}
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uint32_t LatticeSSPI::char_array_to_word(uint8_t *in)
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{
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return static_cast<uint32_t>(in[0] << 24) |
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static_cast<uint32_t>(in[1] << 16) |
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static_cast<uint32_t>(in[2] << 8) |
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static_cast<uint32_t>(in[3] << 0);
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}
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bool LatticeSSPI::EnableISC(uint8_t flash_mode)
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{
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cmd_class_c(ISC_ENABLE);
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if (!pollBusyFlag())
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return false;
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if (!checkStatus(REG_STATUS_ISC_EN, REG_STATUS_ISC_EN))
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return false;
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return true;
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}
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bool LatticeSSPI::DisableISC()
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{
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cmd_class_c(ISC_DISABLE);
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if (!pollBusyFlag())
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return false;
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if (!checkStatus(0, REG_STATUS_ISC_EN))
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return false;
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return true;
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}
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uint32_t LatticeSSPI::readStatusReg()
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{
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uint8_t rx[4];
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cmd_class_a(SSPI_ISC_READ_STATUS, rx, 4 * 8);
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return static_cast<uint64_t>(char_array_to_word(rx));
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}
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/*
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* Read Only command.
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* 8bits command + 24 dummy bits + len rx
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* len: nb bits
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*/
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bool LatticeSSPI::cmd_class_a(uint8_t cmd, uint8_t *rx, uint32_t len)
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{
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const uint32_t xferByteLen = (len + 7) / 8;
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const uint32_t kBytetLen = xferByteLen + 3; // Convert bits to bytes after adding dummy
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uint8_t lrx[kBytetLen];
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uint8_t ltx[kBytetLen];
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memset(ltx, 0x00, kBytetLen);
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_spi->spi_put(cmd, ltx, lrx, kBytetLen);
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memcpy(rx, &lrx[3], xferByteLen);
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return true;
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}
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bool LatticeSSPI::cmd_class_b(uint8_t cmd, uint8_t *tx, uint32_t len)
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{
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throw std::runtime_error("Not implemented");
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return true;
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}
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bool LatticeSSPI::cmd_class_c(uint8_t cmd)
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{
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const uint8_t ltx[3] = {0x00, 0x00, 0x00};
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_spi->spi_put(cmd, ltx, NULL, 3);
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return true;
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}
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uint32_t LatticeSSPI::idCode()
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{
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uint8_t rx[4];
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cmd_class_a(SSPI_READ_ID, rx, 32);
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return char_array_to_word(rx);
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}
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bool LatticeSSPI::pollBusyFlag(bool verbose)
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{
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uint8_t rx;
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int timeout = 0;
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do {
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cmd_class_a(READ_BUSY_FLAG, &rx, 8);
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if (verbose)
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printf("pollBusyFlag :%02x\n", rx);
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if (timeout == 100000000){
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std::cerr << "timeout" << std::endl;
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return false;
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} else {
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timeout++;
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}
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} while (rx != 0);
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return true;
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}
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bool LatticeSSPI::flashErase(uint32_t mask)
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{
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const uint8_t tx[] = {0x01, 0x00, 0x00};
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_spi->spi_put(FLASH_ERASE, tx, 0, 3);
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if (!pollBusyFlag())
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return false;
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if (!checkStatus(0, REG_STATUS_FAIL))
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return false;
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return true;
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}
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bool LatticeSSPI::program_mem()
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{
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bool err;
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LatticeBitParser _bit(_filename, false, _verbose);
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printInfo("Open file: ", false);
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printSuccess("DONE");
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err = _bit.parse();
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printInfo("Parse file: ", false);
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if (err == EXIT_FAILURE) {
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printError("FAIL");
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return false;
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} else {
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printSuccess("DONE");
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}
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if (_verbose)
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_bit.displayHeader();
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/* Prepare bitstream */
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const uint8_t *data = _bit.getData();
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int length = _bit.getLength()/8;
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/* read ID Code 0xE0 and compare to bitstream */
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uint32_t bit_idcode = std::stoul(_bit.getHeaderVal("idcode").c_str(), NULL, 16);
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uint32_t idcode = idCode();
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if (idcode != bit_idcode) {
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char mess[256];
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snprintf(mess, 256, "mismatch between target's idcode and bitstream idcode\n"
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"\tbitstream has 0x%08X hardware requires 0x%08x", bit_idcode, idcode);
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printError(mess);
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return false;
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}
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if (_verbose) {
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printf("IDCode : 0x%08x\n", idcode);
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displayReadReg(readStatusReg());
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}
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/* LSC_REFRESH 0x79 -- "Equivalent to toggle PROGRAMN pin"
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* We REFRESH only if the fpga is in a status of error due to
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* the previous bitstream. For example, this happens if
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* no bitstream is present on the SPI FLASH
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*/
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cmd_class_c(0x79);
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usleep(8000);
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/* ISC Enable 0xC6 */
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printInfo("Enable configuration: ", false);
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if (!EnableISC(0x00)) {
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printError("FAIL");
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displayReadReg(readStatusReg());
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return false;
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} else {
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printSuccess("DONE");
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}
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displayReadReg(readStatusReg());
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/* ISC ERASE
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* For Nexus family (from svf file): 1 byte to tx 0x00
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*/
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printInfo("SRAM erase: ", false);
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//uint32_t mask_erase[1] = {FLASH_ERASE_SRAM};
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if (flashErase(0x01/*mask_erase[0]*/) == false) {
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printError("FAIL");
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displayReadReg(readStatusReg());
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return false;
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} else {
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printSuccess("DONE");
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}
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/* LSC_INIT_ADDRESS */
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cmd_class_c(0x46);
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/* Switch to manual CS.
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* This signal must be low for LSC_BITSTREAM_BURST and
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* all bitstream TX.
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*/
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_spi->setCSmode(FtdiSpi::SPI_CS_MANUAL);
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_spi->clearCs();
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cmd_class_c(0x7A);
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uint8_t tmp[1024];
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int size = 1024;
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ProgressBar progress("Loading", length, 50, _quiet);
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for (int i = 0; i < length; i += size) {
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progress.display(i);
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if (length < i + size) {
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size = length-i;
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}
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for (int ii = 0; ii < size; ii++)
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tmp[ii] = data[i+ii];
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_spi->spi_put(tmp, NULL, size);
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}
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progress.done();
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/* Switch CS to Automatic mode */
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_spi->setCs();
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_spi->setCSmode(FtdiSpi::SPI_CS_AUTO);
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usleep(1000);
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/* disable configuration mode */
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printInfo("Disable configuration: ", false);
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if (!DisableISC()) {
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printError("FAIL");
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displayReadReg(readStatusReg());
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return false;
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} else {
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printSuccess("DONE");
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}
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if (_verbose)
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displayReadReg(readStatusReg());
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uint8_t nop[] = {0xff, 0xff, 0xff, 0xff};
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_spi->spi_put(nop, NULL, 4);
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return true;
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}
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void LatticeSSPI::program(unsigned int offset, bool unprotect_flash)
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{
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bool retval = true;
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if (_mode == FLASH_MODE)
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throw std::runtime_error("Flash mode not avaible when programming in Slave SPI");
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retval = program_mem();
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if (!retval)
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throw std::exception();
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}
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void LatticeSSPI::displayReadReg(uint32_t dev)
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{
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uint8_t err;
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printf("displayReadReg 0x%08x\n", dev);
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if (dev & 1<<0) printf("\tTRAN Mode\n");
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printf("\tConfig Target Selection : %" PRIx32 "\n", (dev >> 1) & 0x07);
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if (dev & 1<<4) printf("\tJTAG Active\n");
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if (dev & 1<<5) printf("\tPWD Protect\n");
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if (dev & 1<<6) printf("\tOTP\n");
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if (dev & 1<<7) printf("\tDecrypt Enable\n");
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if (dev & REG_STATUS_DONE) printf("\tDone Flag\n");
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if (dev & REG_STATUS_ISC_EN) printf("\tISC Enable\n");
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if (dev & 1 << 10) printf("\tWrite Enable\n");
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if (dev & 1 << 11) printf("\tRead Enable\n");
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if (dev & REG_STATUS_BUSY) printf("\tBusy Flag\n");
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if (dev & REG_STATUS_FAIL) printf("\tFail Flag\n");
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if (dev & 1 << 14) printf("\tFFEA OTP\n");
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if (dev & 1 << 15) printf("\tDecrypt Only\n");
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if (dev & 1 << 16) printf("\tPWD Enable\n");
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if (dev & 1 << 17) printf("\tUFM OTP\n");
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if (dev & 1 << 18) printf("\tASSP\n");
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if (dev & 1 << 19) printf("\tSDM Enable\n");
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if (dev & 1 << 20) printf("\tEncryption PreAmble\n");
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if (dev & 1 << 21) printf("\tStd PreAmble\n");
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if (dev & 1 << 22) printf("\tSPIm Fail1\n");
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err = (dev >> 23)&0x07;
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printf("\tBSE Error Code\n");
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printf("\t\t");
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switch (err) {
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case 0:
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printf("No err\n");
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break;
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case 1:
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printf("ID ERR\n");
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break;
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case 2:
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printf("CMD ERR\n");
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break;
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case 3:
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printf("CRC ERR\n");
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break;
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case 4:
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printf("Preamble ERR\n");
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break;
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case 5:
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printf("Abort ERR\n");
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break;
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case 6:
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printf("Overflow ERR\n");
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break;
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case 7:
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printf("SDM EOF\n");
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break;
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case 8:
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printf("Authentication ERR\n");
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break;
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case 9:
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printf("Authentication Setup ERR\n");
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break;
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case 10:
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printf("Bitstream Engine Timeout ERR\n");
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break;
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default:
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printf("unknown error: %x\n", err);
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}
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if (dev & REG_STATUS_EXEC_ERR) printf("\tEXEC Error\n");
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if ((dev >> 27) & 0x01) printf("\tDevice failed to verify\n");
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if ((dev >> 28) & 0x01) printf("\tInvalid Command\n");
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if ((dev >> 29) & 0x01) printf("\tSED Error\n");
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if ((dev >> 30) & 0x01) printf("\tBypass Mode\n");
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if ((dev >> 31) & 0x01) printf("\tFT Mode\n");
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}
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@ -0,0 +1,46 @@
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// SPDX-License-Identifier: Apache-2.0
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/*
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* Copyright (C) 2025 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*/
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#ifndef SRC_LATTICESSPI_HPP_
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#define SRC_LATTICESSPI_HPP_
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#include <string>
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#include "device.hpp"
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#include "ftdispi.hpp"
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class LatticeSSPI: public Device {
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public:
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LatticeSSPI(FtdiSpi *spi, const std::string &filename,
|
||||
const std::string &file_type, const int8_t verbose);
|
||||
|
||||
uint32_t idCode() override;
|
||||
int userCode();
|
||||
void reset() override {}
|
||||
void program(unsigned int offset, bool unprotect_flash) override;
|
||||
|
||||
bool protect_flash(uint32_t len) override { return false; }
|
||||
bool unprotect_flash() override { return false; }
|
||||
bool bulk_erase_flash() override { return false; }
|
||||
|
||||
private:
|
||||
bool program_mem();
|
||||
bool pollBusyFlag(bool verbose=false);
|
||||
uint32_t readStatusReg();
|
||||
void displayReadReg(uint32_t dev);
|
||||
bool EnableISC(uint8_t flash_mode);
|
||||
bool DisableISC();
|
||||
bool flashErase(uint32_t mask);
|
||||
bool checkStatus(uint32_t val, uint32_t mask) {
|
||||
return ((readStatusReg() & mask) == val) ? true : false;
|
||||
}
|
||||
|
||||
bool cmd_class_a(uint8_t cmd, uint8_t *rx, uint32_t len);
|
||||
bool cmd_class_b(uint8_t cmd, uint8_t *tx, uint32_t len);
|
||||
bool cmd_class_c(uint8_t cmd);
|
||||
uint32_t char_array_to_word(uint8_t *in);
|
||||
FtdiSpi *_spi;
|
||||
};
|
||||
#endif /* SRC_LATTICESSPI_HPP_ */
|
||||
|
|
@ -28,6 +28,7 @@
|
|||
#include "gowin.hpp"
|
||||
#include "ice40.hpp"
|
||||
#include "lattice.hpp"
|
||||
#include "latticeSSPI.hpp"
|
||||
#include "libusb_ll.hpp"
|
||||
#include "jtag.hpp"
|
||||
#include "part.hpp"
|
||||
|
|
|
|||
Loading…
Reference in New Issue