Add spiOverJtag for 10CL006YE144C8G + fix for quartus 25

spiOverJtag/Makefile

@@ -17,7 +17,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xcau15p-ffvb676
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
-ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
+ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 10cl006144 \
 	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927 5sgsd5
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
 

spiOverJtag/altclkctrl_inst.v

@@ -0,0 +1,11 @@
+module altclkctrl_inst (
+	input  wire  inclk,
+	input  wire  ena,
+	output wire  outclk
+);
+altclkctrl  u (
+	.inclk(inclk),
+	.ena(ena),
+	.outclk(outclk)
+);
+endmodule

spiOverJtag/build.py

@@ -222,6 +222,7 @@ else:
         "10cl016484" : "10CL016YU484C8G",
         "10cl025256" : "10CL025YU256C8G",
         "10cl055484" : "10CL055YU484C8G",
+        "10cl006144" : "10CL006YE144C8G",
         "ep4cgx15027": "EP4CGX150DF27I7",
         "ep4ce11523" : "EP4CE115F23C7",
         "ep4ce2217"  : "EP4CE22F17C6",
@@ -238,6 +239,8 @@ else:
         "5sgsd5"     : "5SGSMD5K2F40I3"}[part]
     files.append({'name': currDir + 'altera_spiOverJtag.v',
                   'file_type': 'verilogSource'})
+    files.append({'name': currDir + 'altclkctrl_inst.v',
+                  'file_type': 'verilogSource'})
     files.append({'name': currDir + 'altera_spiOverJtag.sdc',
                   'file_type': 'SDC'})
     tool_options = {'device': full_part, 'family':family}