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board: hseda-xc6slx16

This commit is contained in:
Gwenhael Goavec-Merou 2023-03-04 17:55:02 +01:00
parent c35f21a5be
commit cda14f24e3
2 changed files with 8 additions and 0 deletions
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7
doc/boards.yml
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@ -293,6 +293,13 @@
Memory: OK Memory: OK
Flash: IF Flash: IF
- ID: hseda-xc6slx16
Description: XILINX SPARTAN6 XC6SLX16 Microblaze SDRAM USB2.0 FPGA
URL: http://hseda.com/product/xilinx/XC6SLX16/XC6SLX16.htm
FPGA: Spartan6 xc6slx16-ftg256
Memory: OK
Flash: OK
- ID: ice40_generic - ID: ice40_generic
Description: iCEBreaker Description: iCEBreaker
URL: https://1bitsquared.com/collections/fpga/products/icebreaker URL: https://1bitsquared.com/collections/fpga/products/icebreaker

1
src/board.hpp
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@ -150,6 +150,7 @@ static std::map <std::string, target_board_t> board_list = {
SPI_BOARD("gatemate_evb_spi", "colognechip", "gatemate_evb_spi", SPI_BOARD("gatemate_evb_spi", "colognechip", "gatemate_evb_spi",
DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT), DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("hseda-xc6slx16", "xc6slx16ftg256", "", 0, 0, CABLE_DEFAULT),
/* most ice40 boards uses the same pinout */ /* most ice40 boards uses the same pinout */
SPI_BOARD("ice40_generic", "lattice", "ft2232", SPI_BOARD("ice40_generic", "lattice", "ft2232",
DBUS7, DBUS6, 0, DBUS7, DBUS6, 0,