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openFPGALoader
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add efinix Xyloni support (spi mode only)

This commit is contained in:
Gwenhael Goavec-Merou 2021-01-21 07:11:10 +01:00
parent 0e5e609b34
commit cd625d4c99
3 changed files with 10 additions and 2 deletions
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9
README.md
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@ -28,6 +28,7 @@ __Current support kits:__
* [Sipeed Lichee Tang](https://tang.sipeed.com/en/hardware-overview/lichee-tang/) (memory and spi flash) * [Sipeed Lichee Tang](https://tang.sipeed.com/en/hardware-overview/lichee-tang/) (memory and spi flash)
* [Terasic de0nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593) (memory) * [Terasic de0nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593) (memory)
* LambdaConcept ECPIX-5 (memory and flash) * LambdaConcept ECPIX-5 (memory and flash)
* [Efinix Xyloni](https://www.efinixinc.com/products-devkits-xyloni.html) (spi flash (*xyloni_spi*))
__Supported (tested) FPGA:__ __Supported (tested) FPGA:__
@ -436,7 +437,7 @@ tangbit --input /somewhere.bit --svf bitstream.svf
openFPGALoader -b licheeTang /somewhere/*.svf openFPGALoader -b licheeTang /somewhere/*.svf
``` ```
### Firant board (efinix trion T8) ### Firant and Xyloni boards (efinix trion T8)
*.hex* file is the default format generated by *Efinity IDE*, so nothing *.hex* file is the default format generated by *Efinity IDE*, so nothing
special must be done to generates this file. special must be done to generates this file.
@ -448,8 +449,12 @@ __hex file load__
```bash ```bash
openFPGALoader -b fireant /somewhere/project/outflow/*.hex openFPGALoader -b fireant /somewhere/project/outflow/*.hex
``` ```
or, for xyloni board
```bash
openFPGALoader -b xyloni_spi /somewhere/project/outflow/*.hex
```
Since openFPGALoader access the flash directly in SPI mode the *-b fireant* is required (no autodetection possible) Since openFPGALoader access the flash directly in SPI mode the *-b fireant*, *-b xyloni_spi* is required (no autodetection possible)
### ice40 boards (icestick, iCE40-HX8K, iCEBreaker, iCE40HX1K-EVB) ### ice40 boards (icestick, iCE40-HX8K, iCEBreaker, iCE40HX1K-EVB)

2
src/board.hpp
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@ -112,6 +112,8 @@ static std::map <std::string, target_cable_t> board_list = {
JTAG_BITBANG_BOARD("ulx3s", "ft231X", 0, 0, FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS), JTAG_BITBANG_BOARD("ulx3s", "ft231X", 0, 0, FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS),
JTAG_BOARD("ecpix5", "ecpix5-debug", 0, 0), JTAG_BOARD("ecpix5", "ecpix5-debug", 0, 0),
JTAG_BOARD("xtrx", "" , 0, 0), JTAG_BOARD("xtrx", "" , 0, 0),
SPI_BOARD("xyloni_spi", "efinix", "efinix_spi",
DBUS4 | DBUS7, DBUS5, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0),
}; };
#endif #endif

1
src/cable.hpp
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@ -33,6 +33,7 @@ static std::map <std::string, cable_t> cable_list = {
{"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}}, {"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}},
{"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}}, {"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}},
{"dirtyJtag", {MODE_DIRTYJTAG, {}}}, {"dirtyJtag", {MODE_DIRTYJTAG, {}}},
{"efinix_spi", {MODE_FTDI_SERIAL, {0x0403, 0x6011, INTERFACE_A, 0x08, 0x8B, 0x00, 0x00}}},
{"ft2232", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}}, {"ft2232", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}},
{"ft231X", {MODE_FTDI_BITBANG, {0x0403, 0x6015, INTERFACE_A, 0x00, 0x00, 0x00, 0x00}}}, {"ft231X", {MODE_FTDI_BITBANG, {0x0403, 0x6015, INTERFACE_A, 0x00, 0x00, 0x00, 0x00}}},
{"ft232", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}}, {"ft232", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}},