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Merge pull request #265 from devdc/patch-1 

Update boards.yml - added Alchitry Au+
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Gwenhael Goavec-Merou 2022-10-30 15:46:09 +01:00 committed by GitHub
parent 02424ca6cd 2da7696f19
commit c705d638da
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2 changed files with 9 additions and 1 deletions
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7
doc/boards.yml
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@ -20,6 +20,13 @@
Memory: OK Memory: OK
Flash: OK Flash: OK
- ID: alchitry_au_plus
Description: Alchitry Au+ (Plus)
URL: https://www.sparkfun.com/products/17514
FPGA: Artix xc7a100tftg256
Memory: OK
Flash: OK
- ID: arty_a7_35t - ID: arty_a7_35t
Description: Digilent Arty A7 Description: Digilent Arty A7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start

1
src/board.hpp
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@ -105,6 +105,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("ac701", "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("ac701", "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alchitry_au_plus","xc7a100tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
/* left for backward compatibility, use right name instead */ /* left for backward compatibility, use right name instead */
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),