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Add missing sck assignment to xilinxultrascale

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Tomas Šervenikas 2025-05-08 10:22:20 +03:00
parent 3809506900
commit bbc64b9075
1 changed files with 1 additions and 0 deletions
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spiOverJtag/xilinx_spiOverJtag.v
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@ -73,6 +73,7 @@ module spiOverJtag
end end
`ifdef xilinxultrascale `ifdef xilinxultrascale
assign sck = drck;
wire [3:0] di; wire [3:0] di;
assign wpn_dq2 = 1'b1; assign wpn_dq2 = 1'b1;
assign hldn_dq3 = 1'b1; assign hldn_dq3 = 1'b1;