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openFPGALoader
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Merge pull request #486 from mer0m/master 

Flash on primary qspi for Xilinx xcku040 and xcku060 based boards.
This commit is contained in:
Gwenhael Goavec-Merou 2024-09-25 07:26:58 +02:00 committed by GitHub
parent abb64a6aa1 8c03101b93
commit ba6f0fa530
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GPG Key ID: B5690EEEBB952194
9 changed files with 77 additions and 7 deletions
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10
README.md
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@ -61,6 +61,8 @@ openFPGALoader -- a program to flash FPGA
-B, --bridge arg disable spiOverJtag model detection by
providing bitstream(intel/xilinx)
-c, --cable arg jtag interface
--status-pin arg JTAG mode / FTDI: GPIO pin number to use as a
status indicator (active low)
--invert-read-edge JTAG mode / FTDI: read on negative edge
instead of positive
--vid arg probe Vendor ID
@ -71,10 +73,13 @@ openFPGALoader -- a program to flash FPGA
--ftdi-serial arg FTDI chip serial number
--ftdi-channel arg FTDI chip channel number (channels 0-3 map to
A-D)
-d, --device arg device to use (/dev/ttyUSBx)
--detect detect FPGA, add -f to show connected flash
--dfu DFU mode
--dump-flash Dump flash mode
--bulk-erase Bulk erase flash
--enable-quad Enable quad mode for SPI Flash
--disable-quad Disable quad mode for SPI Flash
--target-flash arg for boards with multiple flash chips (some
Xilinx UltraScale boards), select the target
flash: primary (default), secondary or both
@ -89,6 +94,7 @@ openFPGALoader -- a program to flash FPGA
--freq arg jtag frequency (Hz)
-f, --write-flash write bitstream in flash (default: false)
--index-chain arg device index in JTAG-chain
--misc-device arg add JTAG non-FPGA devices <idcode,irlen,name>
--ip arg IP address (XVC and remote bitbang client)
--list-boards list all supported boards
--list-cables list all supported cables
@ -113,10 +119,14 @@ openFPGALoader -- a program to flash FPGA
1:verbose, 2:debug
-h, --help Give this help list
--verify Verify write operation (SPI Flash only)
--xvc Xilinx Virtual Cable Functions
--port arg Xilinx Virtual Cable and remote bitbang Port
(default 3721)
--mcufw arg Microcontroller firmware
--conmcu Connect JTAG to MCU
-D, --read-dna Read DNA (Xilinx FPGA only)
-X, --read-xadc Read XADC (Xilinx FPGA only)
--read-register arg Read Status Register(Xilinx FPGA only)
-V, --Version Print program version
Mandatory or optional arguments to long options are also mandatory or optional

2
doc/FPGAs.yml
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@ -262,7 +262,7 @@ Xilinx:
- xcku115
URL: https://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale.html#productTable
Memory: OK
Flash: NA
Flash: OK (primary)
- Description: Virtex 6
Model:

1
spiOverJtag/Makefile
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@ -16,6 +16,7 @@ XILINX_PARTS := xc3s500evq100 \
xc7k420tffg901 \
xcku3p-ffva676 \
xc7vx330tffg1157 \
xcku040-ffva1156 xcku060-ffva1156 \
xcku5p-ffvb676 \
xcvu9p-flga2104 xcvu37p-fsvh2892
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

17
spiOverJtag/build.py
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@ -93,7 +93,7 @@ if tool in ["ise", "vivado"]:
"xc7a35tfgg484" : "xc7a_fgg484",
"xc7a50tcpg236" : "xc7a_cpg236",
"xc7a50tcsg324" : "xc7a_csg324",
"xc7a50tfgg484" : "xc7a_fgg484",
"xc7a50tfgg484" : "xc7a_fgg484",
"xc7a75tfgg484" : "xc7a_fgg484",
"xc7a100tcsg324" : "xc7a_csg324",
"xc7a100tfgg484" : "xc7a_fgg484",
@ -112,10 +112,12 @@ if tool in ["ise", "vivado"]:
"xc7s25csga225" : "xc7s_csga225",
"xc7s25csga324" : "xc7s_csga324",
"xc7s50csga324" : "xc7s_csga324",
"xcvu9p-flga2104" : "xcvu9p_flga2104",
"xcku040-ffva1156" : "xcku040_ffva1156",
"xcku060-ffva1156" : "xcku060_ffva1156",
"xcvu9p-flga2104" : "xcvu9p_flga2104",
"xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
"xcku3p-ffva676" : "xcku3p_ffva676",
"xcku5p-ffvb676" : "xcku5p_ffvb676",
"xcku3p-ffva676" : "xcku3p_ffva676",
"xcku5p-ffvb676" : "xcku5p_ffvb676",
}[part]
if tool == "ise":
cst_type = "UCF"
@ -172,6 +174,13 @@ if tool in ["ise", "vivado"]:
tool_options = {'part': part + '-2-e'}
elif part == "xcvu37p-fsvh2892":
tool_options = {'part': part + '-2L-e'}
elif part in ["xcku040-ffva1156", "xcku060-ffva1156"]:
tool_options = {'part': part + '-2-e'}
parameters["secondaryflash"]= {
'datatype': 'int',
'paramtype': 'vlogdefine',
'description': 'secondary flash',
'default': 1}
else:
tool_options = {'part': part + '-1'}
cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()

25
spiOverJtag/constr_xcku040_ffva1156.xdc Normal file
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@ -0,0 +1,25 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-5 from UG917
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AC7 - QSPI0_IO0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AB7 - QSPI0_IO1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AA7 - QSPI0_IO2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN Y7 - QSPI0_IO3 Bank 0 - D03_0
# csn - PACKAGE_PIN U7 - QSPI0_CSB Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN AA9 - FPGA_CCLK Bank 0 - CCLK_0
# Secondary QSPI flash
set_property PACKAGE_PIN M20 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN L20 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R21 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R22 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN G26 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65

25
spiOverJtag/constr_xcku060_ffva1156.xdc Normal file
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@ -0,0 +1,25 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-5 from UG917
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block
# sdi_dq0 - PACKAGE_PIN AC7 - QSPI0_IO0 Bank 0 - D00_MOSI_0
# sdo_dq1 - PACKAGE_PIN AB7 - QSPI0_IO1 Bank 0 - D01_DIN_0
# wpn_dq2 - PACKAGE_PIN AA7 - QSPI0_IO2 Bank 0 - D02_0
# hldn_dq3 - PACKAGE_PIN Y7 - QSPI0_IO3 Bank 0 - D03_0
# csn - PACKAGE_PIN U7 - QSPI0_CSB Bank 0 - RDWR_FCS_B_0
# sck - PACKAGE_PIN AA9 - FPGA_CCLK Bank 0 - CCLK_0
# Secondary QSPI flash
set_property PACKAGE_PIN M20 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"] ;# Bank 65 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_D04_65
set_property PACKAGE_PIN L20 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"] ;# Bank 65 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_D05_65
set_property PACKAGE_PIN R21 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"] ;# Bank 65 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_D06_65
set_property PACKAGE_PIN R22 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"] ;# Bank 65 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_D07_65
set_property PACKAGE_PIN G26 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65
set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"] ;# Bank 65 VCCO - VCC1V8 - IO_L2N_T0L_N3_FWE_FCS2_B_65

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spiOverJtag/spiOverJtag_xcku040-ffva1156.bit.gz Normal file
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spiOverJtag/spiOverJtag_xcku060-ffva1156.bit.gz Normal file
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4
src/main.cpp
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@ -865,9 +865,9 @@ int parse_opt(int argc, char **argv, struct arguments *args,
cxxopts::value<std::string>(args->mcufw))
("conmcu", "Connect JTAG to MCU",
cxxopts::value<bool>(args->conmcu))
("D,read_dna", "Read DNA (Xilinx FPGA only)",
("D,read-dna", "Read DNA (Xilinx FPGA only)",
cxxopts::value<bool>(args->read_dna))
("X,read_xadc", "Read XADC (Xilinx FPGA only)",
("X,read-xadc", "Read XADC (Xilinx FPGA only)",
cxxopts::value<bool>(args->read_xadc))
("read-register", "Read Status Register(Xilinx FPGA only)",
cxxopts::value<string>(rd_reg))