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openFPGALoader
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Add pynq-z1 board

This commit is contained in:
Tim Paine 2023-12-08 14:51:38 -05:00
parent 2a2435ecbe
commit b70a3991cc
2 changed files with 8 additions and 0 deletions
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7
doc/boards.yml
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@ -555,6 +555,13 @@
Memory: OK Memory: OK
Flash: OK Flash: OK
- ID: pynq_z1
Description: PYNQ-Z1
URL: https://digilent.com/reference/programmable-logic/pynq-z1/start
FPGA: Zynq7000 xc7z020clg400
Memory: OK
Flash: NA
- ID: pynq_z2 - ID: pynq_z2
Description: PYNQ-Z2 Description: PYNQ-Z2
URL: https://www.tulembedded.com/FPGA/ProductsPYNQ-Z2.html URL: https://www.tulembedded.com/FPGA/ProductsPYNQ-Z2.html

1
src/board.hpp
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@ -186,6 +186,7 @@ static std::map <std::string, target_board_t> board_list = {
DFU_BOARD("orbtrace_dfu", "", "dfu", 0x1209, 0x3442, 1), DFU_BOARD("orbtrace_dfu", "", "dfu", 0x1209, 0x3442, 1),
JTAG_BOARD("papilio_one", "xc3s500evq100", "papilio", 0, 0, CABLE_DEFAULT), JTAG_BOARD("papilio_one", "xc3s500evq100", "papilio", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("pipistrello", "xc6slx45csg324", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("pipistrello", "xc6slx45csg324", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("pynq_z1", "xc7z020clg400", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("pynq_z2", "xc7z020clg400", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("pynq_z2", "xc7z020clg400", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("qmtechCyclone10", "10cl016484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechCyclone10", "10cl016484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "", 0, 0, CABLE_DEFAULT),