mirror of
https://github.com/trabucayre/openFPGALoader.git
synced 2026-08-30 09:59:03 +02:00
xilinx: add support for XC95 CPLD family
This commit is contained in:
Gwenhael Goavec-Merou
+302
-3
@@ -3,6 +3,9 @@
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* Copyright (C) 2019 Gwenhael Goavec-Merou <[email protected]>
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*/
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#include <unistd.h>
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#include <cstring>
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#include <iostream>
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#include <stdexcept>
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#include <string>
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@@ -10,6 +13,7 @@
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#include "jtag.hpp"
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#include "bitparser.hpp"
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#include "configBitstreamParser.hpp"
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#include "jedParser.hpp"
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#include "mcsParser.hpp"
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#include "spiFlash.hpp"
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#include "rawParser.hpp"
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@@ -22,7 +26,7 @@
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Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
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const std::string &file_type,
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Device::prog_type_t prg_type,
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std::string device_package, bool verify, int8_t verbose):
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const std::string &device_package, bool verify, int8_t verbose):
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Device(jtag, filename, file_type, verify, verbose),
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_device_package(device_package)
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{
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@@ -36,10 +40,38 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
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_mode = Device::MEM_MODE;
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else
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_mode = Device::SPI_MODE;
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} else if (_file_extension == "jed") {
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_mode = Device::FLASH_MODE;
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} else {
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_mode = Device::SPI_MODE;
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}
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}
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uint32_t idcode = _jtag->get_target_device_id();
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std::string family = fpga_list[idcode].family;
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if (family.substr(0, 5) == "artix") {
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_fpga_family = ARTIX_FAMILY;
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} else if (family == "spartan7") {
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_fpga_family = SPARTAN7_FAMILY;
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} else if (family == "zynq") {
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_fpga_family = ZYNQ_FAMILY;
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} else if (family == "kintex7") {
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_fpga_family = KINTEX_FAMILY;
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} else if (family == "spartan6") {
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_fpga_family = SPARTAN6_FAMILY;
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} else if (family == "xc9500xl") {
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_fpga_family = XC95_FAMILY;
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if (idcode == 0x59602093)
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_xc95_line_len = 2;
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else if (idcode == 0x59604093)
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_xc95_line_len = 4;
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else if (idcode == 0x59608093)
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_xc95_line_len = 8;
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else if (idcode == 0x59616093)
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_xc95_line_len = 16;
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} else {
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_fpga_family = UNKNOWN_FAMILY;
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}
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}
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Xilinx::~Xilinx() {}
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@@ -52,7 +84,16 @@ Xilinx::~Xilinx() {}
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#define JSTART 0x0C
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#define JSHUTDOWN 0x0D
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#define ISC_DISABLE 0x16
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#define BYPASS 0x3f
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#define BYPASS 0xff
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/* xc95 instructions set */
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#define XC95_IDCODE 0xfe
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#define XC95_ISC_ERASE 0xed
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#define XC95_ISC_ENABLE 0xe9
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#define XC95_ISC_DISABLE 0xf0
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#define XC95_XSC_BLANK_CHECK 0xe5
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#define XC95_ISC_PROGRAM 0xea
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#define XC95_ISC_READ 0xee
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void Xilinx::reset()
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{
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@@ -71,15 +112,31 @@ void Xilinx::reset()
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int Xilinx::idCode()
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{
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int id = 0;
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unsigned char tx_data[4]= {0x00, 0x00, 0x00, 0x00};
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unsigned char rx_data[4];
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_jtag->go_test_logic_reset();
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_jtag->shiftIR(IDCODE, 6);
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_jtag->shiftDR(tx_data, rx_data, 32);
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return ((rx_data[0] & 0x000000ff) |
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id = ((rx_data[0] & 0x000000ff) |
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((rx_data[1] << 8) & 0x0000ff00) |
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((rx_data[2] << 16) & 0x00ff0000) |
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((rx_data[3] << 24) & 0xff000000));
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/* workaround for XC95 with different
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* IR length and IDCODE value
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*/
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if (id == 0) {
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_jtag->go_test_logic_reset();
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_jtag->shiftIR(XC95_IDCODE, 8);
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_jtag->shiftDR(tx_data, rx_data, 32);
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id = ((rx_data[0] & 0x000000ff) |
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((rx_data[1] << 8) & 0x0000ff00) |
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((rx_data[2] << 16) & 0x00ff0000) |
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((rx_data[3] << 24) & 0xff000000));
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}
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return id;
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}
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void Xilinx::program(unsigned int offset)
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@@ -91,6 +148,16 @@ void Xilinx::program(unsigned int offset)
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if (_mode == Device::NONE_MODE || _mode == Device::READ_MODE)
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return;
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if (_mode == Device::FLASH_MODE && _file_extension == "jed") {
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flow_program();
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return;
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}
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if (_fpga_family == XC95_FAMILY) {
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printError("Only jed file and flash mode supported for XC95 CPLD");
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return;
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}
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if (_mode == Device::MEM_MODE)
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reverse = true;
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@@ -288,6 +355,30 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
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bool Xilinx::dumpFlash(const std::string &filename,
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uint32_t base_addr, uint32_t len)
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{
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if (_fpga_family == XC95_FAMILY) {
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/* enable ISC */
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flow_enable();
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std::string buffer = flow_read();
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printInfo("Open dump file ", false);
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FILE *fd = fopen(filename.c_str(), "wb");
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if (!fd) {
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printError("FAIL");
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return false;
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}
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printSuccess("DONE");
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printInfo("Read flash ", false);
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fwrite(buffer.c_str(), sizeof(uint8_t), buffer.size(), fd);
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printSuccess("DONE");
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fclose(fd);
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/* disable ISC */
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flow_disable();
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return true;
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}
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int ret = true;
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/* first need to have bridge in RAM */
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if (load_bridge() == false)
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@@ -310,6 +401,214 @@ bool Xilinx::dumpFlash(const std::string &filename,
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return ret;
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}
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/* */
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/* internal flash (xc95) */
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/* based on ISE xx_1532.bsd files */
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/* */
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void Xilinx::flow_enable()
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{
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uint8_t xfer_buf = 0x15;
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_jtag->shiftIR(XC95_ISC_ENABLE, 8);
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_jtag->shiftDR(&xfer_buf, NULL, 6);
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_jtag->toggleClk(1);
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}
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void Xilinx::flow_disable()
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{
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_jtag->shiftIR(XC95_ISC_DISABLE, 8);
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usleep(100);
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_jtag->shiftIR(BYPASS, 8);
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_jtag->toggleClk(1);
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}
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bool Xilinx::flow_erase()
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{
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uint8_t xfer_buf[3] = {0x03, 0x00, 0x00};
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printInfo("Erase flash ", false);
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_jtag->shiftIR(XC95_ISC_ERASE, 8);
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_jtag->shiftDR(xfer_buf, NULL, 18);
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_jtag->toggleClk(2000000);
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_jtag->shiftDR(NULL, xfer_buf, 18);
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if ((xfer_buf[0] & 0x03) != 0x01) {
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printError("FAIL");
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return false;
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}
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if (_verify) {
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xfer_buf[0] = 0x03;
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xfer_buf[1] = xfer_buf[2] = 0x00;
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_jtag->shiftIR(XC95_XSC_BLANK_CHECK, 8);
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_jtag->shiftDR(xfer_buf, NULL, 18);
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_jtag->toggleClk(500);
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_jtag->shiftDR(NULL, xfer_buf, 18);
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if ((xfer_buf[0] & 0x03) != 0x01) {
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printError("FAIL");
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return false;
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}
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}
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printSuccess("DONE");
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return true;
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}
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bool Xilinx::flow_program()
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{
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uint8_t wr_buf[16+2]; // largest section length
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uint8_t rd_buf[16+3];
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JedParser *jed;
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printInfo("Open file ", false);
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try {
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jed = new JedParser(_filename, _verbose);
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jed->parse();
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} catch (std::exception &e) {
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printError("FAIL");
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return false;
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}
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printSuccess("DONE");
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/* limit JTAG clock frequency to 1MHz */
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if (_jtag->getClkFreq() > 1e6)
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_jtag->setClkFreq(1e6);
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/* enable ISC */
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flow_enable();
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/* erase internal flash */
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if (!flow_erase())
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return false;
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/* xc95 internal flash is written by sector
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* for each one them 15 jed sections are used
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*/
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size_t nb_section = jed->nb_section() / (15);
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ProgressBar progress("Write Flash", nb_section, 50, _quiet);
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for (size_t i = 0; i < nb_section; i++) {
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uint16_t addr2 = i * 32;
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for (int ii = 0; ii < 15; ii++) {
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uint8_t mode = (ii == 14) ? 0x3 : 0x1;
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int id = i * 15 + ii;
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memcpy(wr_buf, jed->data_for_section(id)[0].c_str(),
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_xc95_line_len);
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wr_buf[_xc95_line_len] = (uint8_t) addr2&0xff;
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wr_buf[_xc95_line_len+ 1 ] = (uint8_t)((addr2 >> 8) & 0xff);
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_jtag->shiftIR(XC95_ISC_PROGRAM, 8);
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_jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
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_jtag->shiftDR(wr_buf, NULL, 8 * (_xc95_line_len + 2));
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if (ii == 14)
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_jtag->toggleClk(20000);
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else
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_jtag->toggleClk(1);
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if (ii == 14) {
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mode = 0x00;
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for (int loop_try = 0; loop_try < 32; loop_try++) {
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_jtag->shiftIR(XC95_ISC_PROGRAM, 8);
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_jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
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_jtag->shiftDR(wr_buf, NULL, 8 * (_xc95_line_len + 2));
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_jtag->toggleClk(50000);
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_jtag->shiftDR(NULL, rd_buf, 8 * (_xc95_line_len + 2) + 2);
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if ((rd_buf[0] & 0x03) == 0x01)
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break;
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}
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if ((rd_buf[0] & 0x03) != 0x01) {
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progress.fail();
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return false;
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}
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}
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addr2 += ((ii+1) % 0x05) ? 1 : 4;
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}
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progress.display(i);
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}
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progress.done();
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/* TODO: verify */
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if (_verify) {
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std::string flash = flow_read();
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int flash_pos = 0;
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ProgressBar progress2("Verify Flash", nb_section, 50, _quiet);
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for (size_t section = 0; section < 108; section++) {
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for (size_t subsection = 0; subsection < 15; subsection++) {
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int id = section * 15 + subsection;
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std::string content = jed->data_for_section(id)[0];
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for (int col = 0; col < _xc95_line_len; col++, flash_pos++) {
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if ((uint8_t)content[col] != (uint8_t)flash[flash_pos]) {
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char error[256];
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progress2.fail();
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snprintf(error, sizeof(error),
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"Error: wrong value: read %02x instead of %02x",
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(uint8_t)flash[flash_pos], (uint8_t)content[col]);
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printError(error);
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flow_disable();
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return false;
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}
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}
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}
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}
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progress2.done();
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}
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/* disable ISC */
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flow_disable();
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return true;
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}
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std::string Xilinx::flow_read()
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{
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uint8_t mode;
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std::string buffer;
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uint8_t wr_buf[16+2]; // largest section length
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uint8_t rd_buf[16+2];
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memset(wr_buf, 0xff, 16);
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/* limit JTAG clock frequency to 1MHz */
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if (_jtag->getClkFreq() > 1e6)
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_jtag->setClkFreq(1e6);
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ProgressBar progress("Read Flash", 108, 50, _quiet);
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for (size_t section = 0; section < 108; section++) {
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uint16_t addr2 = section * 32;
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for (int subsection = 0; subsection < 15; subsection++) {
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wr_buf[_xc95_line_len ] = (uint8_t)((addr2 ) & 0xff);
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wr_buf[_xc95_line_len + 1] = (uint8_t)((addr2 >> 8) & 0xff);
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mode = 3;
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_jtag->shiftIR(XC95_ISC_READ, 8);
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_jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
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_jtag->shiftDR(wr_buf, NULL, 8 * (_xc95_line_len + 2));
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_jtag->toggleClk(1);
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mode = 0;
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_jtag->shiftDR(&mode, NULL, 2, Jtag::SHIFT_DR);
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_jtag->shiftDR(NULL, rd_buf, 8 * (_xc95_line_len + 2));
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for (int pos = 0; pos < _xc95_line_len; pos++)
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buffer += rd_buf[pos];
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addr2 += ((subsection+1) % 0x05) ? 1 : 4;
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}
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progress.display(section);
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}
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progress.done();
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return buffer;
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}
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/* */
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/* SPI interface */
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/* */
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/*
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* jtag : jtag interface
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* cmd : opcode for SPI flash
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