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adding nexys A7 (50/100) aka nexys 4 DDR

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This commit is contained in:
Gwenhael Goavec-Merou
2022-11-23 13:47:07 +01:00
parent b1efff805d
commit b078aa393a
2 changed files with 18 additions and 0 deletions
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doc/boards.yml
+16
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@@ -348,6 +348,22 @@
Memory: OK
Flash: OK
- ID: nexys_a7_50
Description: Digilent Nexys A7(Nexys 4 DDR)
URL: https://digilent.com/reference/programmable-logic/nexys-a7/start
FPGA: Artix xc7a50tcsg324
Memory: OK
Flash: OK
Constraints: Nexys4DDR
- ID: nexys_a7_100
Description: Digilent Nexys A7(Nexys 4 DDR)
URL: https://digilent.com/reference/programmable-logic/nexys-a7/start
FPGA: Artix nexys_a7_100
Memory: OK
Flash: OK
Constraints: Nexys4DDR
- ID: nexysVideo
Description: Digilent Nexys Video
URL: https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start
src/board.hpp
+2
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@@ -118,6 +118,8 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("cmod_s7", "xc7s25csga225", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("cmoda7_35t", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("nexys_a7_50", "xc7a50tcsg324", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("nexys_a7_100", "xc7a100tcsg324", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zc702", "xc7z020clg484", "digilent", 0, 0, CABLE_DEFAULT),