Add support for XCVU9P IR length and codes
This commit is contained in:
Ricardo Barbedo
parent
e5481787d8
commit
ad9ad539ff
128
src/xilinx.cpp
128
src/xilinx.cpp
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@ -28,6 +28,76 @@
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#include "pathHelper.hpp"
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#endif
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/* Used for xc3s */
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#define USER1 0x02
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#define CFG_IN 0x05
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#define USERCODE 0x08
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#define IDCODE 0x09
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#define ISC_ENABLE 0x10
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#define JPROGRAM 0x0B
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#define JSTART 0x0C
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#define JSHUTDOWN 0x0D
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#define ISC_PROGRAM 0x11
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#define ISC_DISABLE 0x16
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#define BYPASS 0xff
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/* xc95 instructions set */
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#define XC95_IDCODE 0xfe
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#define XC95_ISC_ERASE 0xed
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#define XC95_ISC_ENABLE 0xe9
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#define XC95_ISC_DISABLE 0xf0
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#define XC95_XSC_BLANK_CHECK 0xe5
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#define XC95_ISC_PROGRAM 0xea
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#define XC95_ISC_READ 0xee
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/* Boundary-scan instruction set based on the FPGA model */
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static std::map<std::string, std::map<std::string, std::vector<uint8_t>>>
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ircode_mapping {
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{
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/* 7-series default */
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"default",
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{
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{ "USER1", {0x02} },
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{ "CFG_IN", {0x05}},
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{ "USERCODE", {0x08} },
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{ "IDCODE", {0x09} },
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{ "ISC_ENABLE", {0x10} },
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{ "JPROGRAM", {0x0B} },
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{ "JSTART", {0x0C} },
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{ "JSHUTDOWN", {0x0D} },
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{ "ISC_PROGRAM", {0x11} },
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{ "ISC_DISABLE", {0x16} },
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{ "BYPASS", {0xff} },
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}
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},
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{
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/* Xilinx Virtex UltraScale+ */
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/* <vivado_dir>/data/parts/xilinx/virtexuplus/public/bsdl/xcvu9p_flga2104.bsd */
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"xcvu9p",
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{
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{ "USER1", {0b00100100, 0b00101001, 0b00} },
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{ "USER2", {0b00100100, 0b00111001, 0b00} },
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{ "CFG_IN", {0b00100100, 0b01011001, 0b00} }, // CFG_IN_SLR1
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{ "USERCODE", {0b00100100, 0b10001001, 0b00} },
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{ "IDCODE", {0b01001001, 0b10010010, 0b00} },
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{ "ISC_ENABLE", {0b00010000, 0b00000100, 0b01} },
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{ "JPROGRAM", {0b11001011, 0b10110010, 0b00} },
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{ "JSTART", {0b00001100, 0b11000011, 0b00} },
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{ "JSHUTDOWN", {0b01001101, 0b11010011, 0b00} },
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{ "ISC_PROGRAM", {0b01010001, 0b00010100, 0b01} },
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{ "ISC_DISABLE", {0b10010110, 0b01100101, 0b01} },
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{ "BYPASS", {0b11111111, 0b11111111, 0b11} },
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}
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}
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};
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/* Helper to get instruction code as a uint8_t pointer * */
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static uint8_t *get_ircode(
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std::map<std::string, std::vector<uint8_t>> &inst_map, std::string inst)
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{
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return inst_map.at(inst).data();
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}
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Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
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const std::string &file_type,
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Device::prog_type_t prg_type,
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@ -55,9 +125,14 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
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}
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}
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_user_instruction = "USER1";
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uint32_t idcode = _jtag->get_target_device_id();
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std::string family = fpga_list[idcode].family;
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std::string model = fpga_list[idcode].model;
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_irlen = fpga_list[idcode].irlength;
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_ircode_map = ircode_mapping.at("default");
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if (family.substr(0, 5) == "artix") {
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_fpga_family = ARTIX_FAMILY;
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} else if (family == "spartan7") {
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@ -78,6 +153,7 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
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_fpga_family = KINTEXUS_FAMILY;
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} else if (family == "virtexusp") {
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_fpga_family = VIRTEXUSP_FAMILY;
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_ircode_map = ircode_mapping.at(model);
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} else if (family.substr(0, 8) == "spartan3") {
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_fpga_family = SPARTAN3_FAMILY;
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if (_mode != Device::MEM_MODE) {
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@ -176,38 +252,17 @@ bool Xilinx::zynqmp_init(const std::string &family)
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return true;
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}
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#define USER1 0x02
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#define CFG_IN 0x05
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#define USERCODE 0x08
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#define IDCODE 0x09
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#define ISC_ENABLE 0x10
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#define JPROGRAM 0x0B
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#define JSTART 0x0C
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#define JSHUTDOWN 0x0D
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#define ISC_PROGRAM 0x11
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#define ISC_DISABLE 0x16
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#define BYPASS 0xff
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/* xc95 instructions set */
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#define XC95_IDCODE 0xfe
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#define XC95_ISC_ERASE 0xed
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#define XC95_ISC_ENABLE 0xe9
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#define XC95_ISC_DISABLE 0xf0
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#define XC95_XSC_BLANK_CHECK 0xe5
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#define XC95_ISC_PROGRAM 0xea
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#define XC95_ISC_READ 0xee
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void Xilinx::reset()
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{
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_jtag->shiftIR(JSHUTDOWN, 6);
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_jtag->shiftIR(JPROGRAM, 6);
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_jtag->shiftIR(get_ircode(_ircode_map, "JSHUTDOWN"), NULL, _irlen);
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_jtag->shiftIR(get_ircode(_ircode_map, "JPROGRAM"), NULL, _irlen);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(10000*12);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(2000);
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_jtag->shiftIR(BYPASS, 6);
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_jtag->shiftIR(get_ircode(_ircode_map, "BYPASS"), NULL, _irlen);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(2000);
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}
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@ -218,7 +273,8 @@ int Xilinx::idCode()
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unsigned char tx_data[4]= {0x00, 0x00, 0x00, 0x00};
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unsigned char rx_data[4];
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_jtag->go_test_logic_reset();
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_jtag->shiftIR(IDCODE, 6);
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_jtag->shiftIR(get_ircode(_ircode_map, "IDCODE"), NULL, _irlen);
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_jtag->shiftDR(tx_data, rx_data, 32);
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id = ((rx_data[0] & 0x000000ff) |
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((rx_data[1] << 8) & 0x0000ff00) |
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@ -372,7 +428,9 @@ void Xilinx::program_spi(ConfigBitstreamParser * bit, unsigned int offset,
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void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
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{
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std::cout << "load program" << std::endl;
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unsigned char tx_buf, rx_buf;
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unsigned char *tx_buf;
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unsigned char rx_buf[(_irlen >> 3) + 1];
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/* comment TDI TMS TCK
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* 1: On power-up, place a logic 1 on the TMS,
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* and clock the TCK five times. This ensures X 1 5
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@ -392,12 +450,12 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
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* TCK five times. This ensures starting in X 1 5
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* the TLR (Test-Logic-Reset) state.
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*/
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_jtag->shiftIR(JPROGRAM, 6);
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_jtag->shiftIR(get_ircode(_ircode_map, "JPROGRAM"), NULL, _irlen);
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/* test */
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tx_buf = BYPASS;
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tx_buf = get_ircode(_ircode_map, "BYPASS");
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do {
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_jtag->shiftIR(&tx_buf, &rx_buf, 6);
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} while (!(rx_buf &0x01));
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_jtag->shiftIR(tx_buf, rx_buf, _irlen);
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} while (!(rx_buf[0] &0x01));
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/*
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* 8: Move into the RTI state. X 0 10,000(1)
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*/
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@ -410,7 +468,7 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
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* exiting SHIFT-IR, as defined in the 0 1 1
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* IEEE standard.
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*/
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_jtag->shiftIR(CFG_IN, 6);
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_jtag->shiftIR(get_ircode(_ircode_map, "CFG_IN"), NULL, _irlen);
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/*
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* 11: Enter the SELECT-DR state. X 1 2
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*/
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@ -462,7 +520,7 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
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* 20: Load the last bit of the JSTART instruction. 0 1 1
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* 21: Move to the UPDATE-IR state. X 1 1
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*/
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_jtag->shiftIR(JSTART, 6, Jtag::UPDATE_IR);
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_jtag->shiftIR(get_ircode(_ircode_map, "JSTART"), NULL, _irlen, Jtag::UPDATE_IR);
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/*
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* 22: Move to the RTI state and clock the
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* startup sequence by applying a minimum X 0 2000
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@ -1329,7 +1387,7 @@ int Xilinx::spi_put(uint8_t cmd,
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jtx[i+1] = McsParser::reverseByte(tx[i]);
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}
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/* addr BSCAN user1 */
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_jtag->shiftIR(USER1, 6);
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_jtag->shiftIR(get_ircode(_ircode_map, _user_instruction), NULL, _irlen);
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/* send first already stored cmd,
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* in the same time store each byte
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* to next
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@ -1353,7 +1411,7 @@ int Xilinx::spi_put(uint8_t *tx, uint8_t *rx, uint32_t len)
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jtx[i] = McsParser::reverseByte(tx[i]);
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}
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/* addr BSCAN user1 */
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_jtag->shiftIR(USER1, 6);
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_jtag->shiftIR(get_ircode(_ircode_map, _user_instruction), NULL, _irlen);
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/* send first already stored cmd,
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* in the same time store each byte
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* to next
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@ -1376,7 +1434,7 @@ int Xilinx::spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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uint8_t tx = McsParser::reverseByte(cmd);
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uint32_t count = 0;
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_jtag->shiftIR(USER1, 6, Jtag::UPDATE_IR);
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_jtag->shiftIR(get_ircode(_ircode_map, _user_instruction), NULL, _irlen, Jtag::UPDATE_IR);
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_jtag->shiftDR(&tx, NULL, 8, Jtag::SHIFT_DR);
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do {
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@ -193,6 +193,8 @@ class Xilinx: public Device, SPIInterface {
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uint16_t _cpld_addr_size; /**< number of addr bits */
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char _cpld_base_name[7]; /**< cpld name (without package size) */
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int _irlen; /**< IR bit length */
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std::map<std::string, std::vector<uint8_t>> _ircode_map; /**< bscan instructions based on model */
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std::string _user_instruction; /* which USER bscan instruction to interface with SPI */
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};
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#endif
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