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Merge pull request #422 from antmicro/tmichalak/antmicro-ddr-tester-boards 

Add support for Antmicro's DDR tester board
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Gwenhael Goavec-Merou 2024-01-25 18:50:29 +01:00 committed by GitHub
parent 308e47c5c0 d2f31860cd
commit abda6ed72c
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7 changed files with 42 additions and 1 deletions
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21
doc/boards.yml
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@ -62,6 +62,27 @@
Memory: SVF
Flash: SVF
- ID: antmicro_ddr4_tester
Description: Antmicro Data Center DRAM Tester
URL: https://opensource.antmicro.com/projects/data-center-dram-tester
FPGA: Kintex7 xc7k160t
Memory: OK
Flash: OK
- ID: antmicro_ddr5_tester
Description: Antmicro DDR5 Tester
URL: https://opensource.antmicro.com/projects/ddr5-tester
FPGA: Kintex7 xc7k160t
Memory: OK
Flash: OK
- ID: antmicro_lpddr4_tester
Description: Antmicro LPDDR4 Test Board
URL: https://opensource.antmicro.com/projects/lpddr4-test-board
FPGA: Kintex7 xc7k70t
Memory: OK
Flash: OK
- ID: arty_a7_35t
Description: Digilent Arty A7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start

2
spiOverJtag/Makefile
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@ -8,7 +8,7 @@ XILINX_PARTS := xc3s500evq100 \
xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
xc7a200tsbg484 xc7a200tfbg484 \
xc7s25csga225 xc7s25csga324 xc7s50csga324 \
xc7k70tfbg676 \
xc7k70tfbg484 xc7k70tfbg676 \
xc7k160tffg676 \
xc7k325tffg676 xc7k325tffg900 \
xc7k420tffg901 \

1
spiOverJtag/build.py
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@ -88,6 +88,7 @@ if tool in ["ise", "vivado"]:
"xc7a100tfgg676" : "xc7a_fgg676",
"xc7a200tsbg484" : "xc7a_sbg484",
"xc7a200tfbg484" : "xc7a_fbg484",
"xc7k70tfbg484" : "xc7k_fbg484",
"xc7k70tfbg676" : "xc7k_fbg676",
"xc7k160tffg676" : "xc7k_ffg676",
"xc7k325tffg676" : "xc7k_ffg676",

6
spiOverJtag/constr_xc7k_fbg484.ucf Normal file
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@ -0,0 +1,6 @@
NET "csn" LOC = L18 | IOSTANDARD = LVCMOS33;
NET "sdi_dq0" LOC = H18 | IOSTANDARD = LVCMOS33;
NET "sdo_dq1" LOC = H19 | IOSTANDARD = LVCMOS33;
NET "wpn_dq2" LOC = G18 | IOSTANDARD = LVCMOS33;
NET "hldn_dq3" LOC = F19 | IOSTANDARD = LVCMOS33;

10
spiOverJtag/constr_xc7k_fbg484.xdc Normal file
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@ -0,0 +1,10 @@
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]

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spiOverJtag/spiOverJtag_xc7k70tfbg484.bit.gz Normal file
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3
src/board.hpp
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@ -111,6 +111,9 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("alinx_ax516", "xc6slx16csg324", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7101", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr5_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_lpddr4_tester", "xc7k70tfbg484", "ft4232", 0, 0, CABLE_DEFAULT),
/* left for backward compatibility, use right name instead */
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),