XADC_dna: clean code

src/main.cpp

@@ -553,7 +553,8 @@ int main(int argc, char **argv)
 		if (fab == "xilinx") {
 			fpga = new Xilinx(jtag, args.bit_file, args.secondary_bit_file,
 				args.file_type, args.prg_type, args.fpga_part, args.bridge_path,
-				args.target_flash, args.verify, args.verbose, args.skip_load_bridge, args.skip_reset, args.read_dna, args.read_xadc);
+				args.target_flash, args.verify, args.verbose, args.skip_load_bridge, args.skip_reset,
+				args.read_dna, args.read_xadc);
 		} else if (fab == "altera") {
 			fpga = new Altera(jtag, args.bit_file, args.file_type,
 				args.prg_type, args.fpga_part, args.bridge_path, args.verify,
@@ -816,9 +817,9 @@ int parse_opt(int argc, char **argv, struct arguments *args,
 				cxxopts::value<std::string>(args->mcufw))
 			("conmcu", "Connect JTAG to MCU",
 				cxxopts::value<bool>(args->conmcu))
-			("D,read_dna", "Read DNA",
+			("D,read_dna", "Read DNA (Xilinx FPGA only)",
 				cxxopts::value<bool>(args->read_dna))
-			("X,read_xadc", "Read XADC",
+			("X,read_xadc", "Read XADC (Xilinx FPGA only)",
 				cxxopts::value<bool>(args->read_xadc))
 			("V,Version", "Print program version");
 

src/part.hpp

@@ -86,9 +86,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03736093, {"xilinx", "zynq",     "xc7z100", 6}},
 
 	/* Xilinx Ultrascale / Kintex */
-	{0x13919093, {"xilinx", "kintexus", "xcku060", 6}},
-	{0x13822093, {"xilinx", "kintexus", "xcku040", 6}},
 	{0x13823093, {"xilinx", "kintexus", "xcku035", 6}},
+	{0x13822093, {"xilinx", "kintexus", "xcku040", 6}},
+	{0x13919093, {"xilinx", "kintexus", "xcku060", 6}},
 	{0x1390d093, {"xilinx", "kintexus", "xcku115", 6}},
 
 	/* Xilinx Ultrascale+ / Artix */

src/xilinx.cpp

@@ -54,7 +54,7 @@
 #define XC95_ISC_READ        0xee
 
 /* DRP instructions set */
-#define XADC_DRP 0x37 //110111
+#define XADC_DRP 0x37
 
 /* XADC Addresses */
 #define XADC_TEMP     0x00
@@ -193,15 +193,13 @@ static void open_bitfile(
 	printSuccess("DONE");
 }
 
-#define FUSE_DNA   0x32 //110010
+#define FUSE_DNA	0x32
 
 unsigned long long Xilinx::fuse_dna_read(void)
 {
 	unsigned char tx_data[8] = {0,0,0,0,0,0,0,0};
 	unsigned char rx_data[8];
 
-       //tx_data = htonl(tx_data);
-
 	_jtag->go_test_logic_reset();
 	_jtag->shiftIR(FUSE_DNA, 6);
 	_jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 64);
@@ -215,6 +213,7 @@ unsigned long long Xilinx::fuse_dna_read(void)
 		}
 		dna = (dna << 8ULL) | rev;
 	}
+
 	return dna & 0x1ffffffffffffff;
 }
 
@@ -223,7 +222,6 @@ unsigned int Xilinx::xadc_read(unsigned short addr)
 	unsigned int tx_data = (1 << 26) | (addr << 16);
 	unsigned int rx_data = 0;
 
-
 	_jtag->go_test_logic_reset();
 	_jtag->shiftIR(XADC_DRP, 6);
 	_jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 32);
@@ -231,7 +229,6 @@ unsigned int Xilinx::xadc_read(unsigned short addr)
 	_jtag->shiftIR(XADC_DRP, 6);
 	_jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 32);
 
-
 	return rx_data;
 }
 
@@ -240,7 +237,6 @@ void Xilinx::xadc_write(unsigned short addr, unsigned short data)
 	unsigned int tx_data = (1 << 26) | (addr << 16) | data;
 	unsigned int rx_data = 0;
 
-
 	_jtag->go_test_logic_reset();
 	_jtag->shiftIR(XADC_DRP, 6);
 	_jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 32);
@@ -398,7 +394,6 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 
 	if (read_xadc) {
 		if (_fpga_family == ARTIX_FAMILY || _fpga_family == KINTEXUS_FAMILY) {
-
 			// calibrate XADC
 			Xilinx::xadc_single(8);
 
@@ -425,12 +420,12 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 			}
 
 			/* output as JSON dict */
-
 			std::cout << "{";
 			std::cout << "\"temp\": " << temp << ", ";
 			std::cout << "\"raw\":  {";
 			for (int ch = 0; ch < MAX_CHANNEL; ch++) {
-                               std::cout << "\"" << ch << "\": " << channel_values[ch] << ((ch==MAX_CHANNEL-1)? "}" : ", ");
+				std::cout << "\"" << ch << "\": " << channel_values[ch]
+					 << ((ch==MAX_CHANNEL-1)? "}" : ", ");
 			}
 			std::cout << "}" << std::endl;