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ALINX AX7102 board.

This commit is contained in:
Haakan T Johansson 2023-10-24 14:03:18 +02:00
parent fd8497026a
commit a87d689d83
2 changed files with 8 additions and 0 deletions
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7
doc/boards.yml
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@ -41,6 +41,13 @@
Memory: OK Memory: OK
Flash: OK Flash: OK
- ID: alinx_ax7102
Description: ALINX AX/7102
URL: https://alinx.com/en/detail/493
FPGA: Artix xc7a100tfgg484
Memory: OK
Flash: OK
- ID: analogMax - ID: analogMax
Description: Trenz TEI0010 - AnalogMax Description: Trenz TEI0010 - AnalogMax
URL: https://wiki.trenz-electronic.de/display/PD/TEI0010+-+AnalogMax URL: https://wiki.trenz-electronic.de/display/PD/TEI0010+-+AnalogMax

1
src/board.hpp
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@ -109,6 +109,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alchitry_au_plus","xc7a100tftg256", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alchitry_au_plus","xc7a100tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax516", "xc6slx16csg324", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alinx_ax516", "xc6slx16csg324", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
/* left for backward compatibility, use right name instead */ /* left for backward compatibility, use right name instead */
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),