lattice: added ECP3 family support (SRAM only)
This commit is contained in:
Gwenhael Goavec-Merou
parent
3d7cb14195
commit
a7b56c3732
329
src/lattice.cpp
329
src/lattice.cpp
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@ -12,7 +12,9 @@
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#include <string.h>
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#include <unistd.h>
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#include <iomanip>
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#include <iostream>
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#include <list>
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#include <stdexcept>
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#include "jtag.hpp"
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@ -141,6 +143,17 @@ using namespace std;
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#define PUBKEY_LENGTH_BYTES 64 /* length of the public key (MachXO3D) in bytes */
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/* ECP3 */
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#define ECP3_LSCC_BITSTREAM_BURST 0x02
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#define ECP3_ISC_ERASE 0x03 /* ISC_ERASE */
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#define ECP3_ISC_ENABLE 0x15
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#define ECP3_IDCODE 0x16
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#define ECP3_READ_USERCODE 0x17
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#define ECP3_ISC_PROGRAM_USERCODE 0x1A
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#define ECP3_RESET_ADDRESS 0x21
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#define ECP3_LSCC_REFRESH 0x23
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#define ECP3_READ_STATUS_REGISTER 0x53
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Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
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Device::prog_type_t prg_type, std::string flash_sector, bool verify, int8_t verbose, bool skip_load_bridge, bool skip_reset):
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Device(jtag, filename, file_type, verify, verbose),
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@ -203,6 +216,8 @@ Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
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printError("Unknown flash sector");
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throw std::exception();
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}
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} else if (family == "ECP3") {
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_fpga_family = ECP3_FAMILY;
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} else if (family == "ECP5") {
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_fpga_family = ECP5_FAMILY;
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} else if (family == "CrosslinkNX") {
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@ -270,6 +285,7 @@ bool Lattice::checkStatus(uint64_t val, uint64_t mask)
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bool Lattice::program_mem()
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{
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bool err;
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LatticeBitParser _bit(_filename, false, _verbose);
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printInfo("Open file: ", false);
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@ -308,14 +324,21 @@ bool Lattice::program_mem()
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* PRELOAD/SAMPLE 0x1C
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* For NEXUS family fpgas, the Bscan register is 362 bits long or
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* 45.25 bytes => 46 bytes
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* For ECP3 family fpgas, the Bscan register is 1077 bits long or
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* 134.62 bytes => 135 bytes
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*/
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uint8_t tx_buf[46];
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memset(tx_buf, 0xff, 46);
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uint8_t tx_buf[135];
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memset(tx_buf, 0xff, 135);
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int tx_len;
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if(_fpga_family == NEXUS_FAMILY){
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tx_len = 46;
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} else {
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tx_len = 26;
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switch (_fpga_family) {
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case NEXUS_FAMILY:
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tx_len = 46;
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break;
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case ECP3_FAMILY:
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tx_len = 135;
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break;
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default:
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tx_len = 26;
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}
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wr_rd(PRELOAD_SAMPLE, tx_buf, tx_len, NULL, 0);
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@ -326,32 +349,41 @@ bool Lattice::program_mem()
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*/
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/*flag to understand if we refreshed or not*/
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bool was_refreshed;
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if (_fpga_family == NEXUS_FAMILY) {
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if (!checkStatus(0, REG_STATUS_PRV_CNF_CHK_MASK)) {
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printInfo("Error in previous bitstream execution. REFRESH: ", false);
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wr_rd(REFRESH, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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/* In Lattice FPGA-TN-02099 document in a note it's reported that there
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is a delay time after LSC_REFRESH where "Duration could be in
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seconds". Without whis waiting time, busy flag can't be cleared.*/
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sleep(5);
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was_refreshed = true;
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switch (_fpga_family) {
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case NEXUS_FAMILY:
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if (!checkStatus(0, REG_STATUS_PRV_CNF_CHK_MASK)) {
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printError("FAIL");
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displayReadReg(readStatusReg());
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return false;
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printInfo("Error in previous bitstream execution. REFRESH: ", false);
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wr_rd(REFRESH, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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/* In Lattice FPGA-TN-02099 document in a note it's reported that there
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is a delay time after LSC_REFRESH where "Duration could be in
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seconds". Without whis waiting time, busy flag can't be cleared.*/
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sleep(5);
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was_refreshed = true;
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if (!checkStatus(0, REG_STATUS_PRV_CNF_CHK_MASK)) {
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printError("FAIL");
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displayReadReg(readStatusReg());
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return false;
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} else {
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printSuccess("DONE");
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}
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} else {
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printSuccess("DONE");
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was_refreshed = false;
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if (_verbose){
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printInfo("No error in previous bitstream execution.", true);
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}
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}
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} else {
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break;
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case ECP3_FAMILY:
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wr_rd(ECP3_LSCC_REFRESH, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(5, 1);
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usleep_ecp3(500000); // 0.5s
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was_refreshed = false;
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break;
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default:
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was_refreshed = false;
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if (_verbose){
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printInfo("No error in previous bitstream execution.", true);
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}
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}
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} else {
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was_refreshed = false;
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}
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/* ISC Enable 0xC6 */
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@ -387,6 +419,11 @@ bool Lattice::program_mem()
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printSuccess("DONE");
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}
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if (_fpga_family == ECP3_FAMILY) {
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if (!write_userCode(0xffffffff))
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return false;
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}
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/* ISC ERASE
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* For Nexus family (from svf file): 1 byte to tx 0x00
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*/
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@ -404,15 +441,43 @@ bool Lattice::program_mem()
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}
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/* LSC_INIT_ADDRESS */
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wr_rd(0x46, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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if (_fpga_family == ECP3_FAMILY) {
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wr_rd(ECP3_RESET_ADDRESS, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(5);
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usleep_ecp3(2000); // 2ms
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/* read user code (User Code register must have all bit set cleared) */
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const uint32_t dummy = 0xffffffff;
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uint32_t rx = 0;
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wr_rd(ECP3_READ_USERCODE, (uint8_t *)&dummy, 4, (uint8_t *)&rx, 4);
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if (rx != 0x00000000) {
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char message[256];
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snprintf(message, 256, "failed: 0x%08x instead of 0xffffffff", rx);
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printError(message);
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return false;
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}
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} else {
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wr_rd(0x46, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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}
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const uint8_t *data = _bit.getData();
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int length = _bit.getLength()/8;
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wr_rd(0x7A, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(2);
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if (_fpga_family == ECP3_FAMILY) {
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/* Reset Address */
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wr_rd(ECP3_RESET_ADDRESS, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(5, 1);
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usleep_ecp3(2000); // 2ms
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wr_rd(ECP3_LSCC_BITSTREAM_BURST, NULL, 0, NULL, 0);
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} else {
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wr_rd(0x7A, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(2);
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}
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uint8_t tmp[1024];
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int size = 1024;
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@ -431,27 +496,45 @@ bool Lattice::program_mem()
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for (int ii = 0; ii < size; ii++)
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tmp[ii] = ConfigBitstreamParser::reverseByte(data[i+ii]);
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_jtag->shiftDR(tmp, NULL, size*8, next_state);
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_jtag->shiftDR(tmp, NULL, size * 8, next_state);
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}
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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uint32_t status_mask;
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if (_fpga_family == MACHXO3D_FAMILY)
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status_mask = REG_STATUS_MACHXO3D_CNF_CHK_MASK;
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else
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status_mask = REG_STATUS_CNF_CHK_MASK;
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if (_fpga_family == ECP3_FAMILY) {
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_jtag->toggleClk(256, 1);
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usleep_ecp3(2000);
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if (checkStatus(0, status_mask)) {
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/* Verifiy User Code register */
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uint32_t rx = userCode();
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if (rx != 0x00000000) {
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progress.fail();
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char message[256];
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snprintf(message, 256, "failed: 0x%08x instead of 0x00000000", rx);
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printError(message);
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return false;
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}
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progress.done();
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} else {
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progress.fail();
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displayReadReg(readStatusReg());
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return false;
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}
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_jtag->toggleClk(1000);
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wr_rd(0xff, NULL, 0, NULL, 0);
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uint32_t status_mask;
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if (_fpga_family == MACHXO3D_FAMILY)
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status_mask = REG_STATUS_MACHXO3D_CNF_CHK_MASK;
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else
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status_mask = REG_STATUS_CNF_CHK_MASK;
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if (checkStatus(0, status_mask)) {
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progress.done();
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} else {
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progress.fail();
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displayReadReg(readStatusReg());
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return false;
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}
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/* bypass */
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wr_rd(0xff, NULL, 0, NULL, 0);
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}
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if (_verbose)
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printf("userCode: %08x\n", userCode());
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@ -468,6 +551,25 @@ bool Lattice::program_mem()
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printSuccess("DONE");
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}
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if (_fpga_family == ECP3_FAMILY) {
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/* Bypass */
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wr_rd(0xff, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(100, 1);
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usleep_ecp3(1000);
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// Verify STATUS Register
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uint64_t status = readStatusReg();
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_jtag->toggleClk(5, 1);
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if ((status & 0x60007) != 0x20000) {
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char message[256];
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snprintf(message, 256, "Programming failed: status 0x%" PRIx64 "instead of 0x20000", status);
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printError(message);
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displayReadReg(status);
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return false;
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}
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}
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if (_verbose)
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displayReadReg(readStatusReg());
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@ -898,6 +1000,14 @@ void Lattice::program(unsigned int offset, bool unprotect_flash)
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*/
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bool Lattice::EnableISC(uint8_t flash_mode)
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{
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if (_fpga_family == ECP3_FAMILY) {
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wr_rd(ECP3_ISC_ENABLE, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(5, 1);
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usleep_ecp3(20000); // 0.20s
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return true;
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}
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wr_rd(ISC_ENABLE, &flash_mode, 1, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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@ -911,6 +1021,13 @@ bool Lattice::EnableISC(uint8_t flash_mode)
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bool Lattice::DisableISC()
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{
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if (_fpga_family == ECP3_FAMILY) {
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/** Shift in ISC DISABLE instruction */
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_jtag->shiftIR(0x1E, 8, Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(5, 1);
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usleep_ecp3(200000);
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return true;
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}
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wr_rd(ISC_DISABLE, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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@ -942,7 +1059,8 @@ bool Lattice::DisableCfg()
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uint32_t Lattice::idCode()
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{
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uint8_t device_id[4];
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wr_rd(READ_DEVICE_ID_CODE, NULL, 0, device_id, 4);
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const uint8_t idcode = (_fpga_family == ECP3_FAMILY) ? ECP3_IDCODE : READ_DEVICE_ID_CODE;
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wr_rd(idcode, NULL, 0, device_id, 4);
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return device_id[3] << 24 |
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device_id[2] << 16 |
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device_id[1] << 8 |
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@ -952,13 +1070,40 @@ uint32_t Lattice::idCode()
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int Lattice::userCode()
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{
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uint8_t usercode[4];
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wr_rd(0xC0, NULL, 0, usercode, 4);
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wr_rd((_fpga_family == ECP3_FAMILY) ? ECP3_READ_USERCODE : 0xC0,
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NULL, 0, usercode, 4);
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return usercode[3] << 24 |
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usercode[2] << 16 |
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usercode[1] << 8 |
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usercode[0];
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}
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bool Lattice::write_userCode(uint32_t usercode)
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{
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// ! Shift in ISC PROGRAM USERCODE(0x1A) instruction
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// SIR 8 TDI (1A);
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// SDR 32 TDI (FFFFFFFF);
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// RUNTEST IDLE 5 TCK 2,00E-03 SEC;
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// ! Shift in READ USERCODE(0x17) instruction
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// SIR 8 TDI (17);
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// SDR 32 TDI (FFFFFFFF)
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// TDO (FFFFFFFF);
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wr_rd(ECP3_ISC_PROGRAM_USERCODE, (uint8_t *)&usercode, 4, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(5, 1);
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usleep_ecp3(2000); // 2ms
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uint32_t rd_usercode = userCode();
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if (rd_usercode != usercode) {
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char message[256];
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snprintf(message, 256, "failed: 0x%08x instead of 0x%08x",
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rd_usercode, usercode);
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printError(message);
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return false;
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}
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return true;
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}
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bool Lattice::checkID()
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{
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printf("\n");
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@ -1005,12 +1150,13 @@ uint64_t Lattice::readStatusReg()
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uint64_t reg;
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uint8_t rx[8], tx[8];
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int reg_len = get_statusreg_size() / 8;
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const int reg_len = get_statusreg_size() / 8;
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const uint8_t regcode = (_fpga_family == ECP3_FAMILY) ? ECP3_READ_STATUS_REGISTER : READ_STATUS_REGISTER;
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/* valgrind warn */
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memset(tx, 0, 8);
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memset(rx, 0, 8);
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wr_rd(READ_STATUS_REGISTER, tx, reg_len, rx, reg_len);
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wr_rd(regcode, tx, reg_len, rx, reg_len);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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reg = (uint64_t) rx[7] << 56 | (uint64_t) rx[6] << 48 | (uint64_t) rx[5] << 40 | (uint64_t) rx[4] << 32 | rx[3] << 24 | rx[2] << 16 | rx[1] << 8 | rx[0];
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@ -1052,8 +1198,75 @@ bool Lattice::wr_rd(uint8_t cmd,
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return true;
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}
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typedef struct {
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std::string description;
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uint8_t offset;
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uint8_t size;
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std::map<int, std::string> reg_cnt;
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} reg_struct_t;
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#define REG_ENTRY(_description, _offset, _size, ...) \
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{_description, _offset, _size, {__VA_ARGS__}}
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static const std::map<std::string, std::list<reg_struct_t>> reg_content = {
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{"StatusRegister", std::list<reg_struct_t>{
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REG_ENTRY("CRC Error", 0, 1, {0, "OK"}, {1, "KO"}),
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REG_ENTRY("ID Verify failed", 1, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Invalid Command", 2, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("SPIm Mode Error", 3, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Device locked", 4, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Key Fire", 5, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Alignement Preamble", 6, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Encryption Preamble", 7, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Std Preamble", 8, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("HFC", 9, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Memory Cleared", 15, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Device Secured", 16, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Device Configured", 17, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Non-JTAG Mode", 18, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("ReadBack Mode", 19, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Bypass Mode", 20, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Flow Trough", 21, 1, {0, "No"}, {1, "Yes"}),
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REG_ENTRY("Configuration Mode", 22, 1, {0, "No"}, {1, "Yes"}),
|
||||
REG_ENTRY("Transparent Mode", 23, 1, {0, "No"}, {1, "Yes"}),
|
||||
}},
|
||||
};
|
||||
|
||||
void Lattice::displayReadReg(uint64_t dev)
|
||||
{
|
||||
if (_fpga_family == ECP3_FAMILY) {
|
||||
auto reg = reg_content.find("StatusRegister");
|
||||
if (reg == reg_content.end()) {
|
||||
printError("Unknown register StatusRegister");
|
||||
return;
|
||||
}
|
||||
|
||||
std::stringstream raw_val;
|
||||
raw_val << "0x" << std::hex << dev;
|
||||
printSuccess("Register raw value: " + raw_val.str());
|
||||
|
||||
const std::list<reg_struct_t> regs = reg->second;
|
||||
for (reg_struct_t r: regs) {
|
||||
uint8_t offset = r.offset;
|
||||
uint8_t size = r.size;
|
||||
uint32_t mask = (1 << size) - 1;
|
||||
uint32_t val = (dev >> offset) & mask;
|
||||
std::stringstream ss, desc;
|
||||
desc << r.description;
|
||||
ss << std::setw(20) << std::left << r.description;
|
||||
if (r.reg_cnt.size() != 0) {
|
||||
ss << r.reg_cnt[val];
|
||||
} else {
|
||||
std::stringstream hex_val;
|
||||
hex_val << "0x" << std::hex << val;
|
||||
ss << hex_val.str();
|
||||
}
|
||||
|
||||
printInfo(ss.str());
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t err;
|
||||
printf("displayReadReg\n");
|
||||
if (dev & 1<<0) printf("\tTRAN Mode\n");
|
||||
|
|
@ -1247,6 +1460,12 @@ bool Lattice::flashErase(uint32_t mask)
|
|||
(uint8_t)((mask >> 16) & 0xff)
|
||||
};
|
||||
wr_rd(FLASH_ERASE, tx, 2, NULL, 0);
|
||||
} else if (_fpga_family == ECP3_FAMILY) {
|
||||
wr_rd(ECP3_ISC_ERASE, NULL, 0, NULL, 0);
|
||||
_jtag->set_state(Jtag::RUN_TEST_IDLE);
|
||||
_jtag->toggleClk(5, 1);
|
||||
usleep_ecp3(2000000); // 2s
|
||||
return true;
|
||||
} else {
|
||||
uint8_t tx[1] = {(uint8_t)(mask & 0xff)};
|
||||
wr_rd(FLASH_ERASE, tx, 1, NULL, 0);
|
||||
|
|
@ -1540,6 +1759,14 @@ int Lattice::spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*************************** MODS FOR ECP3 ************************************/
|
||||
|
||||
void Lattice::usleep_ecp3(uint64_t us_time)
|
||||
{
|
||||
const uint32_t clk_period = 1e9/static_cast<float>(_jtag->getClkFreq());
|
||||
const uint32_t clk_len = (us_time * 1000) / clk_period;
|
||||
_jtag->toggleClk(clk_len, 0); // 0.5s
|
||||
}
|
||||
|
||||
/*************************** MODS FOR MacXO3D *********************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ class Lattice: public Device, SPIInterface {
|
|||
int8_t verbose, bool skip_load_bridge, bool skip_reset);
|
||||
uint32_t idCode() override;
|
||||
int userCode();
|
||||
bool write_userCode(uint32_t usercode);
|
||||
void reset() override;
|
||||
void program(unsigned int offset, bool unprotect_flash) override;
|
||||
bool program_mem();
|
||||
|
|
@ -74,6 +75,7 @@ class Lattice: public Device, SPIInterface {
|
|||
MACHXO3D_FAMILY = 2,
|
||||
ECP5_FAMILY = 3,
|
||||
NEXUS_FAMILY = 4,
|
||||
ECP3_FAMILY,
|
||||
UNKNOWN_FAMILY = 999
|
||||
};
|
||||
|
||||
|
|
@ -122,6 +124,9 @@ class Lattice: public Device, SPIInterface {
|
|||
/* test */
|
||||
bool checkID();
|
||||
|
||||
/************************* MODS for ECP3 ******************************/
|
||||
void usleep_ecp3(uint64_t us_time);
|
||||
|
||||
/*********************** MODS FOR MacXO3D *****************************/
|
||||
enum lattice_flash_sector_t {
|
||||
LATTICE_FLASH_UNDEFINED = 0,
|
||||
|
|
|
|||
Loading…
Reference in New Issue