gowin: added (undocumented) sequence to be performed when CRC Error bit is set

This commit is contained in:
Gwenhael Goavec-Merou 2025-07-20 10:23:19 +02:00
parent 42a4801180
commit a53aedb137
2 changed files with 38 additions and 0 deletions

View File

@ -922,7 +922,10 @@ bool Gowin::eraseSRAM()
send_command(READ_IDCODE);
send_command(NOOP);
_jtag->toggleClk(125 * 8);
} else if (is_gw2a) {
gw2a_force_state();
}
do {
if (!enableCfg()) {
@ -960,6 +963,7 @@ bool Gowin::eraseSRAM()
must_loop = false;
loop++;
}
} while(must_loop);
if (_mode == Device::FLASH_MODE) {
@ -1188,6 +1192,31 @@ bool Gowin::dumpFlash(uint32_t base_addr, uint32_t len)
return post_flash_access() && ret;
}
void Gowin::gw2a_force_state()
{
/* undocumented sequence but required when
* flash failure
*/
uint32_t state = readStatusReg();
if ((state & STATUS_CRC_ERROR) == 0)
return;
send_command(CONFIG_DISABLE);
send_command(0);
idCode();
state = readStatusReg();
send_command(CONFIG_DISABLE);
send_command(0);
state = readStatusReg();
idCode();
send_command(CONFIG_ENABLE);
reset();
send_command(CONFIG_DISABLE);
send_command(NOOP);
idCode();
send_command(NOOP);
idCode();
}
bool Gowin::prepare_flash_access()
{
/* Work around FPGA stuck in Bad Command status */
@ -1196,6 +1225,7 @@ bool Gowin::prepare_flash_access()
_jtag->set_state(Jtag::RUN_TEST_IDLE);
_jtag->toggleClk(1000000);
}
if (!eraseSRAM()) {
printError("Error: fail to erase SRAM");
return false;

View File

@ -52,6 +52,14 @@ class Gowin: public Device, SPIInterface {
int spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
uint32_t timeout, bool verbose) override;
/* -------------- */
/* Arora specific */
/* -------------- */
/*!
* \brief undocumented sequence required after an SPI flash failure (CRC Bit set)
*/
void gw2a_force_state();
/* ---------------- */
/* Arora V specific */
/* ---------------- */