gowin: added (undocumented) sequence to be performed when CRC Error bit is set
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@ -922,7 +922,10 @@ bool Gowin::eraseSRAM()
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send_command(READ_IDCODE);
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send_command(READ_IDCODE);
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send_command(NOOP);
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send_command(NOOP);
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_jtag->toggleClk(125 * 8);
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_jtag->toggleClk(125 * 8);
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} else if (is_gw2a) {
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gw2a_force_state();
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}
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}
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do {
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do {
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if (!enableCfg()) {
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if (!enableCfg()) {
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@ -960,6 +963,7 @@ bool Gowin::eraseSRAM()
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must_loop = false;
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must_loop = false;
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loop++;
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loop++;
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}
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}
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} while(must_loop);
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} while(must_loop);
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if (_mode == Device::FLASH_MODE) {
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if (_mode == Device::FLASH_MODE) {
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@ -1188,6 +1192,31 @@ bool Gowin::dumpFlash(uint32_t base_addr, uint32_t len)
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return post_flash_access() && ret;
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return post_flash_access() && ret;
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}
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}
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void Gowin::gw2a_force_state()
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{
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/* undocumented sequence but required when
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* flash failure
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*/
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uint32_t state = readStatusReg();
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if ((state & STATUS_CRC_ERROR) == 0)
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return;
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send_command(CONFIG_DISABLE);
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send_command(0);
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idCode();
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state = readStatusReg();
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send_command(CONFIG_DISABLE);
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send_command(0);
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state = readStatusReg();
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idCode();
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send_command(CONFIG_ENABLE);
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reset();
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send_command(CONFIG_DISABLE);
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send_command(NOOP);
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idCode();
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send_command(NOOP);
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idCode();
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}
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bool Gowin::prepare_flash_access()
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bool Gowin::prepare_flash_access()
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{
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{
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/* Work around FPGA stuck in Bad Command status */
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/* Work around FPGA stuck in Bad Command status */
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@ -1196,6 +1225,7 @@ bool Gowin::prepare_flash_access()
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000000);
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_jtag->toggleClk(1000000);
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}
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}
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if (!eraseSRAM()) {
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if (!eraseSRAM()) {
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printError("Error: fail to erase SRAM");
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printError("Error: fail to erase SRAM");
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return false;
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return false;
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@ -52,6 +52,14 @@ class Gowin: public Device, SPIInterface {
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int spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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int spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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uint32_t timeout, bool verbose) override;
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uint32_t timeout, bool verbose) override;
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/* -------------- */
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/* Arora specific */
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/* -------------- */
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/*!
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* \brief undocumented sequence required after an SPI flash failure (CRC Bit set)
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*/
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void gw2a_force_state();
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/* ---------------- */
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/* ---------------- */
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/* Arora V specific */
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/* Arora V specific */
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/* ---------------- */
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/* ---------------- */
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