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Add Support for Xilinx Artix-7 a25t (xc7a25t)

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nulltek 2023-04-07 15:28:29 +12:00
parent a43f94fcf5
commit 9aa0e72afb
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GPG Key ID: 0F841C22395D0E62
9 changed files with 31 additions and 0 deletions
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1
doc/FPGAs.yml
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@ -182,6 +182,7 @@ Xilinx:
- Description: Artix 7
Model:
- xc7a25t
- xc7a35ti
- xc7a50t
- xc7a75t

1
spiOverJtag/Makefile
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@ -1,5 +1,6 @@
XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
xc6slx150tfgg484 xc6slx150tcsg484 \
xc7a25tcpg238 xc7a25tcsg325 \
xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
xc7a50tcsg324 xc7a50tcpg236 xc7a75tfgg484 \
xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\

2
spiOverJtag/build.py
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@ -72,6 +72,8 @@ if tool in ["ise", "vivado"]:
"xc6slx100fgg484" : "xc6s_fgg484",
"xc6slx150tcsg484" : "xc6s_csg484",
"xc6slx150tfgg484" : "xc6s_fgg484",
"xc7a25tcpg238" : "xc7a_cpg238",
"xc7a25tcsg325" : "xc7a_csg325",
"xc7a35tcpg236" : "xc7a_cpg236",
"xc7a35tcsg324" : "xc7a_csg324",
"xc7a35tftg256" : "xc7a_ftg256",

11
spiOverJtag/constr_xc7a_cpg238.xdc Normal file
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@ -0,0 +1,11 @@
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];

11
spiOverJtag/constr_xc7a_csg325.xdc Normal file
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@ -0,0 +1,11 @@
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];

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spiOverJtag/spiOverJtag_xc7a25tcpg238.bit.gz Normal file
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spiOverJtag/spiOverJtag_xc7a25tcsg325.bit.gz Normal file
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4
spiOverJtag/xilinx_spiOverJtag.tcl
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@ -7,6 +7,8 @@ file delete -force $build_path
# Project creation
set grade [dict create \
xc7a25tcpg238 -1 \
xc7a25tcsg325 -1 \
xc7a35tcpg236 -1 \
xc7a35tcsg324 -1 \
xc7a35tftg256 -1 \
@ -21,6 +23,8 @@ set grade [dict create \
]
set pkg_name [dict create \
xc7a25tcpg238 xc7a_cpg238 \
xc7a25tcsg325 xc7a_csg325 \
xc7a35tcpg236 xc7a_cpg236 \
xc7a35tcsg324 xc7a_csg324 \
xc7a35tftg256 xc7a_ftg256 \

1
src/part.hpp
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@ -22,6 +22,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
{0x0a014c35, {"anlogic", "eagle s20", "EG4S20BG256", 8}},
{0x00004c37, {"anlogic", "elf2", "EF2M45", 8}},
{0x037c2093, {"xilinx", "artix a7 25t", "xc7a25", 6}},
{0x0362D093, {"xilinx", "artix a7 35t", "xc7a35", 6}},
{0x0362c093, {"xilinx", "artix a7 50t", "xc7a50t", 6}},
{0x03632093, {"xilinx", "artix a7 75t", "xc7a75t", 6}},