Start support for Virtex6.

spiOverJtag/Makefile

@@ -1,5 +1,6 @@
 XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
 	xc6slx150tfgg484 \
+	xc6vlx130tff784 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
 	xc7a50tcsg324 xc7a50tcpg236 xc7a75tfgg484 \
 	xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\

spiOverJtag/build.py

@@ -55,6 +55,10 @@ elif subpart == "xc3s":
     family = "Spartan3E"
     tool = "ise"
     speed = -4
+elif subpart == "xc6v":
+    family = "Virtex6"
+    tool = "ise"
+    speed = -1
 elif subpart == "xcvu":
     family = "Virtex UltraScale"
     tool = "vivado"
@@ -71,6 +75,7 @@ if tool in ["ise", "vivado"]:
         "xc6slx45csg324"   : "xc6s_csg324",
         "xc6slx100fgg484"  : "xc6s_fgg484",
         "xc6slx150tfgg484" : "xc6s_fgg484",
+        "xc6vlx130tff784"  : "xc6v_ff784",
         "xc7a35tcpg236"    : "xc7a_cpg236",
         "xc7a35tcsg324"    : "xc7a_csg324",
         "xc7a35tftg256"    : "xc7a_ftg256",
@@ -102,6 +107,7 @@ if tool in ["ise", "vivado"]:
                             "xc6slx45csg324":   "xc6slx45",
                             "xc6slx100fgg484":  "xc6slx100",
                             "xc6slx150tfgg484": "xc6slx150t",
+                            "xc6vlx130tff784"  : "xc6vlx130t",
                             "xc7k325tffg676":   "xc7k325t",
                             "xc7k325tffg900":   "xc7k325t",
                             "xc7k420tffg901":   "xc7k420t",
@@ -114,6 +120,8 @@ if tool in ["ise", "vivado"]:
                             "xc6slx45csg324":   "csg324",
                             "xc6slx100fgg484":  "fgg384",
                             "xc6slx150tfgg484": "fgg484",
+                            "xc6vlx130tff784":  "ff784",
+                            "xc7k325tffg676":   "xc7k325t",
                             "xc7k325tffg676":   "ffg676",
                             "xc7k325tffg900":   "ffg900",
                             "xc7k420tffg901":   "ffg901",

spiOverJtag/constr_xc6v_ff784.ucf

@@ -0,0 +1,6 @@
+CONFIG VCCAUX = "2.5";
+
+NET "sdi_dq0"  LOC = H6   | IOSTANDARD = LVCMOS25;
+NET "sdo_dq1"  LOC = AF6  | IOSTANDARD = LVCMOS25;
+NET "csn"      LOC = AE24 | IOSTANDARD = LVCMOS25;
+NET "sck"      LOC = AH6  | IOSTANDARD = LVCMOS25;

spiOverJtag/xilinx_spiOverJtag.v

@@ -8,6 +8,9 @@ module spiOverJtag
 `endif
 `ifdef spartan3e
 	output sck,
+`endif
+`ifdef virtex6
+	output sck,
 `endif
 	output sdi_dq0,
 	input  sdo_dq1,
@@ -51,7 +54,10 @@ module spiOverJtag
 		end
 	end
 
+// STARTUP primitives
+
 `ifndef virtexultrascale
+`ifndef virtex6
 `ifdef spartan6
 	assign sck = drck;
 `else
@@ -79,6 +85,29 @@ module spiOverJtag
 	);
 `endif
 `endif
+`else // virtex6
+	wire di;
+	wire sck = drck;
+	STARTUP_VIRTEX6 #(
+		.PROG_USR("FALSE")
+	) startup_virtex6_inst (
+		.EOS(),
+		.CLK(1'b0),       // unused
+		.GSR(1'b0),       // unused
+		.GTS(1'b0),       // unused
+		.USRCCLKO (sck),  // user FPGA -> CCLK pin
+		.USRCCLKTS(1'b0), // drive CCLK not in high-Z
+		.USRDONEO (1'b1), // why both USRDONE are high?
+		.USRDONETS(1'b1), // ??
+		.TCKSPI(),        // echo of CCLK from TCK pin
+		.DINSPI(di),      // data from SPI flash
+		.CFGMCLK(),       // unused
+		.CFGCLK(),        // unused
+		.PREQ(),          // unused
+		.PACK(1'b0),      // tied low for 'safe' operations
+		.KEYCLEARB(1'b0)  // not used
+	);
+`endif
 `else // virtexultrascale
 	wire [3:0] di;
 	assign sdo_dq1 = di[1];
@@ -114,6 +143,8 @@ module spiOverJtag
 	);
 `endif
 
+// BSCAN primitives
+
 `ifdef spartan3e
 	BSCAN_SPARTAN3 bscane2_inst (
 		.CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.
@@ -133,10 +164,14 @@ module spiOverJtag
 		.TDO2   ()         // 1-bit input: USER2 function
 	);
 `else
+`ifdef virtex6
+	BSCAN_VIRTEX6 #(
+`else
 `ifdef spartan6
 	BSCAN_SPARTAN6 #(
 `else
 	BSCANE2 #(
+`endif
 `endif
 		.JTAG_CHAIN(1)  // Value for USER command.
 	) bscane2_inst (

src/xilinx.cpp

@@ -54,6 +54,21 @@
 /* Boundary-scan instruction set based on the FPGA model */
 static std::map<std::string, std::map<std::string, std::vector<uint8_t>>>
 	ircode_mapping {
+		{	"virtex6",
+			{
+				{ "USER1",       {0b11000010, 0b11} },
+				{ "CFG_IN",      {0b11000101, 0b11} },
+				{ "USERCODE",    {0b11001000, 0b11} },
+				{ "IDCODE",      {0b11001001, 0b11} },
+				{ "ISC_ENABLE",  {0b11010000, 0b11} },
+				{ "JPROGRAM",    {0b11001011, 0b11} },
+				{ "JSTART",      {0b11001100, 0b11} },
+				{ "JSHUTDOWN",   {0b11001101, 0b11} },
+				{ "ISC_PROGRAM", {0b11010001, 0b11} },
+				{ "ISC_DISABLE", {0b11010111, 0b11} },
+				{ "BYPASS",      {0b11111111, 0b11} },
+			}
+		},
 		{
 			/* 7-series default */
 			"default",
@@ -208,6 +223,9 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		}
 	} else if (family == "spartan6") {
 		_fpga_family = SPARTAN6_FAMILY;
+	} else if (family == "virtex6") {
+		_fpga_family = VIRTEX6_FAMILY;
+		_ircode_map = ircode_mapping.at("virtex6");
 	} else if (family == "xc2c") {
 		xc2c_init(idcode);
 	} else if (family == "xc9500xl") {

src/xilinx.hpp

@@ -164,6 +164,7 @@ class Xilinx: public Device, SPIInterface {
 			ZYNQMP_FAMILY,
 			XCF_FAMILY,
 			VIRTEXUSP_FAMILY,
+			VIRTEX6_FAMILY,
 			UNKNOWN_FAMILY  = 999
 		};