xilinx: use shiftIR with val when it's possible
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1afeb22478
commit
9391b7840d
12
xilinx.cpp
12
xilinx.cpp
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@ -43,10 +43,9 @@ void Xilinx::reset()
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int Xilinx::idCode()
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int Xilinx::idCode()
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{
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{
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unsigned char tx_data = IDCODE;
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unsigned char rx_data[4];
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unsigned char rx_data[4];
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_jtag->go_test_logic_reset();
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_jtag->go_test_logic_reset();
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_jtag->shiftIR(&tx_data, NULL, 6);
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_jtag->shiftIR(IDCODE, 6);
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_jtag->shiftDR(NULL, rx_data, 32);
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_jtag->shiftDR(NULL, rx_data, 32);
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return ((rx_data[0] & 0x000000ff) |
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return ((rx_data[0] & 0x000000ff) |
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((rx_data[1] << 8) & 0x0000ff00) |
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((rx_data[1] << 8) & 0x0000ff00) |
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@ -78,8 +77,7 @@ void Xilinx::program(unsigned int offset)
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* TCK five times. This ensures starting in X 1 5
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* TCK five times. This ensures starting in X 1 5
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* the TLR (Test-Logic-Reset) state.
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* the TLR (Test-Logic-Reset) state.
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*/
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*/
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tx_buf = JPROGRAM;
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_jtag->shiftIR(JPROGRAM, 6);
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_jtag->shiftIR(&tx_buf, NULL, 6/*, FtdiJtag::TEST_LOGIC_RESET*/);
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/* test */
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/* test */
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tx_buf = BYPASS;
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tx_buf = BYPASS;
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do {
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do {
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@ -97,8 +95,7 @@ void Xilinx::program(unsigned int offset)
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* exiting SHIFT-IR, as defined in the 0 1 1
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* exiting SHIFT-IR, as defined in the 0 1 1
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* IEEE standard.
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* IEEE standard.
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*/
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*/
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tx_buf = CFG_IN;
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_jtag->shiftIR(CFG_IN, 6);
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_jtag->shiftIR(&tx_buf, NULL, 6);
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/*
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/*
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* 11: Enter the SELECT-DR state. X 1 2
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* 11: Enter the SELECT-DR state. X 1 2
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*/
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*/
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@ -133,8 +130,7 @@ void Xilinx::program(unsigned int offset)
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* 20: Load the last bit of the JSTART instruction. 0 1 1
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* 20: Load the last bit of the JSTART instruction. 0 1 1
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* 21: Move to the UPDATE-IR state. X 1 1
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* 21: Move to the UPDATE-IR state. X 1 1
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*/
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*/
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tx_buf = JSTART;
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_jtag->shiftIR(JSTART, 6, FtdiJtag::UPDATE_IR);
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_jtag->shiftIR(&tx_buf, NULL, 6, FtdiJtag::UPDATE_IR);
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/*
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/*
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* 22: Move to the RTI state and clock the
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* 22: Move to the RTI state and clock the
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* startup sequence by applying a minimum X 0 2000
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* startup sequence by applying a minimum X 0 2000
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