add support for colorlight-i9+ board + spiOverJtag/spiOverJtag_xc7a50tfgg484.bit.gz

doc/boards.yml

@@ -181,6 +181,13 @@
   Flash: OK
   Constraints: Colorlight-i9-v7.2
 
+- ID: colorlight-i9+
+  Description: Colorlight I9+
+  URL: https://www.colorlight-led.tech/colorlight-i9-2/
+  FPGA: Artix xc7a50tfgg484
+  Memory: OK
+  Flash: OK
+
 - ID: crosslinknx_evn
   Description: Lattice CrossLink-NX Evaluation Board
   URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CrossLink-NXEvaluationBoard

spiOverJtag/Makefile

@@ -4,7 +4,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xc6slx150tfgg484 xc6slx150tcsg484 \
 	xc7a25tcpg238 xc7a25tcsg325 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
-	xc7a50tcsg324 xc7a50tcpg236 xc7a75tfgg484 \
+	xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \
 	xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
 	xc7a200tsbg484 xc7a200tfbg484 \
 	xc7s25csga225 xc7s25csga324 xc7s50csga324 \

spiOverJtag/build.py

@@ -80,6 +80,7 @@ if tool in ["ise", "vivado"]:
         "xc7a35tftg256"    : "xc7a_ftg256",
         "xc7a50tcpg236"    : "xc7a_cpg236",
         "xc7a50tcsg324"    : "xc7a_csg324",
+        "xc7a50tfgg484"	   : "xc7a_fgg484",
         "xc7a75tfgg484"    : "xc7a_fgg484",
         "xc7a100tcsg324"   : "xc7a_csg324",
         "xc7a100tfgg484"   : "xc7a_fgg484",

src/board.hpp

@@ -125,6 +125,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("colorlight",      "", "",           0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("colorlight-i5",   "", "cmsisdap", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("colorlight-i9",   "", "cmsisdap", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("colorlight-i9+",  "xc7a50tfgg484", "",        0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("cyc1000",         "10cl025256", "ft2232",     0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("c10lp-refkit",    "10cl055484", "ft2232",     0, 0, CABLE_DEFAULT),