spiOverJtag,bpiOverJtag: integrates bpi mode in build.py and adds a Makefile in bpiOverJtag

bpiOverJtag/.gitignore

@@ -0,0 +1,6 @@
+tmp_*
+*.bit
+*.rbf
+vivado*.jou
+vivado*.log
+.Xil

bpiOverJtag/Makefile

@@ -0,0 +1,14 @@
+BPI_XILINX_PARTS     := xc7k480tffg1156
+BPI_XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix bpiOverJtag_, $(BPI_XILINX_PARTS)))
+
+BIT_FILES := $(BPI_XILINX_BIT_FILES)
+
+all: $(BIT_FILES)
+
+$(BPI_XILINX_BIT_FILES) : bpiOverJtag_%.bit.gz : tmp_%/bpiOverJtag.bit
+
+tmp_%/bpiOverJtag.bit : xilinx_bpiOverJtag.v bpiOverJtag_core.v
+	../spiOverJtag/build.py $* bpi
+
+clean:
+	-rm -rf tmp_* *.jou *.log .Xil

bpiOverJtag/build_bpi_xc7k480t.tcl

@@ -1,46 +0,0 @@
-# Vivado TCL script to build bpiOverJtag for xc7k480tffg1156
-# Run with: vivado -mode batch -source build_bpi_xc7k480t.tcl
-
-set part "xc7k480tffg1156-2"
-set project_name "bpiOverJtag_xc7k480tffg1156"
-set output_dir "./output_bpi_xc7k480t"
-
-# Create output directory
-file mkdir $output_dir
-
-# Create in-memory project
-create_project -in_memory -part $part
-
-# Add source files
-read_verilog bpiOverJtag_core.v
-read_verilog xilinx_bpiOverJtag.v
-
-# Add constraints
-read_xdc constr_xc7k480t_bpi_ffg1156.xdc
-
-# Synthesize
-synth_design -top bpiOverJtag -part $part
-
-# Optimize
-opt_design
-
-# Place
-place_design
-
-# Route
-route_design
-
-# Generate reports
-report_utilization -file $output_dir/utilization.rpt
-report_timing_summary -file $output_dir/timing.rpt
-
-# Write bitstream
-write_bitstream -force $output_dir/$project_name.bit
-
-# Close project
-close_project
-
-puts "Bitstream generated: $output_dir/$project_name.bit"
-puts ""
-puts "To install, run:"
-puts "  gzip -c $output_dir/$project_name.bit > bpiOverJtag_xc7k480tffg1156.bit.gz"

spiOverJtag/Makefile

@@ -36,7 +36,7 @@ tmp_efinix_%/efinix_spiOverJtag.bit : efinix_spiOverJtag.v
 $(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit
 
 tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v spiOverJtag_core.v
-	./build.py $*
+	./build.py $* spi
 
 $(ALTERA_BIT_FILES): spiOverJtag_%.rbf.gz: tmp_%/spiOverJtag.rbf
 	gzip -9 -c $< > $@
@@ -44,7 +44,7 @@ tmp_%/spiOverJtag.rbf: tmp_%/spiOverJtag.sof
 	quartus_cpf --option=bitstream_compression=off -c $< $@
 
 tmp_%/spiOverJtag.sof: altera_spiOverJtag.v
-	./build.py $*
+	./build.py $* spi
 
 clean:
 	-rm -rf tmp_* *.jou *.log .Xil

spiOverJtag/build.py

@@ -37,10 +37,14 @@ packages = {
     },
 }
 
-if len(os.sys.argv) != 2:
+if len(os.sys.argv) != 3 :
-    print("missing board param")
+    print("missing board flash type params")
     os.sys.exit()
-part = os.sys.argv[1]
+part       = os.sys.argv[1]
+flash_type = os.sys.argv[2]
+
+# Check file type keyword
+assert flash_type in ["spi", "bpi"]
 
 build_dir="tmp_" + part
 if not os.path.isdir(build_dir):
@@ -84,7 +88,7 @@ elif subpart == "xc7v":
     tool = "vivado"
 elif subpart == "xc7k":
     device_size = int(part.split('k')[1].split('t')[0])
-    if device_size <= 160:
+    if flash_type == "bpi" or device_size <= 160:
         family = "Kintex 7"
         tool = "vivado"
     else:
@@ -214,10 +218,13 @@ if tool in ["ise", "vivado"]:
             tool_options = {'part': part + '-1'}
 
     cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()
-    files.append({'name': currDir + 'xilinx_spiOverJtag.v',
+    files.append({'name': os.path.join(currDir, f"xilinx_{flash_type}OverJtag.v"),
                   'file_type': 'verilogSource'})
     files.append({'name': cst_file, 'file_type': cst_type})
 else:
+    # Altera only support SPI mode.
+    assert flash_type in ["spi"]
+
     full_part = {
         "10cl016484" : "10CL016YU484C8G",
         "10cl025256" : "10CL025YU256C8G",
@@ -245,7 +252,7 @@ else:
                   'file_type': 'SDC'})
     tool_options = {'device': full_part, 'family':family}
 
-files.append({'name': currDir + 'spiOverJtag_core.v',
+files.append({'name': os.path.join(currDir, f"{flash_type}OverJtag_core.v"),
               'file_type': 'verilogSource'})
 
 parameters[family.lower().replace(' ', '')]= {
@@ -254,11 +261,11 @@ parameters[family.lower().replace(' ', '')]= {
     'description': 'fpga family',
     'default': 1}
 
-edam = {'name' : "spiOverJtag",
+edam = {'name' : f"{flash_type}OverJtag",
         'files': files,
         'tool_options': {tool: tool_options},
         'parameters': parameters,
-        'toplevel' : 'spiOverJtag',
+        'toplevel' : f"{flash_type}OverJtag",
 }
 
 backend = get_edatool(tool)(edam=edam, work_root=build_dir)
@@ -271,14 +278,14 @@ if tool in ["vivado", "ise"]:
     import gzip
 
     # Compress bitstream.
-    with open(f"tmp_{part}/spiOverJtag.bit", 'rb') as bit:
+    with open(f"tmp_{part}/{flash_type}OverJtag.bit", 'rb') as bit:
-        with gzip.open(f"spiOverJtag_{part}.bit.gz", 'wb', compresslevel=9) as bit_gz:
+        with gzip.open(f"{flash_type}OverJtag_{part}.bit.gz", 'wb', compresslevel=9) as bit_gz:
             shutil.copyfileobj(bit, bit_gz)
 
     # Create Symbolic links for all supported packages.
     if family in ["Artix", "Spartan 7"]:
-        in_file = f"spiOverJtag_{part}.bit.gz"
+        in_file = f"{flash_type}OverJtag_{part}.bit.gz"
         for pkg in packages[family][part]:
-            out_file = f"spiOverJtag_{part}{pkg}.bit.gz"
+            out_file = f"{flash_type}OverJtag_{part}{pkg}.bit.gz"
             if not os.path.exists(out_file):
                 subprocess.run(["ln", "-s", in_file, out_file])