drop div_by_5 to allow 2.5MHz clock
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01ac90a172
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85f9791600
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@ -346,7 +346,6 @@ int FTDIpp_MPSSE::init(unsigned char latency, unsigned char bitmask_mode,
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int FTDIpp_MPSSE::setClkFreq(uint32_t clkHZ)
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int FTDIpp_MPSSE::setClkFreq(uint32_t clkHZ)
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{
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{
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int ret;
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int ret;
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bool use_divide_by_5;
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uint8_t buffer[4] = { TCK_DIVISOR, 0x00, 0x00};
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uint8_t buffer[4] = { TCK_DIVISOR, 0x00, 0x00};
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uint32_t base_freq;
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uint32_t base_freq;
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float real_freq = 0;
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float real_freq = 0;
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@ -357,43 +356,23 @@ int FTDIpp_MPSSE::setClkFreq(uint32_t clkHZ)
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/* FT2232C has no divide by 5 instruction
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/* FT2232C has no divide by 5 instruction
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* and default freq is 12MHz
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* and default freq is 12MHz
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*/
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*/
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if (_ftdi->type != TYPE_2232C) {
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if (_ftdi->type == TYPE_2232C) {
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base_freq = 60000000;
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/* use full speed only when freq > 6MHz
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* => more freq resolution using
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* 2^16 to describe 0 -> 6MHz
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*/
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if (clkHZ > 6000000) {
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use_divide_by_5 = false;
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if ((ret = mpsse_store(DIS_DIV_5)) < 0)
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return ret;
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} else {
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use_divide_by_5 = true;
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base_freq /= 5;
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if ((ret = mpsse_store(EN_DIV_5)) < 0)
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return ret;
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}
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} else {
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base_freq = 12000000;
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base_freq = 12000000;
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use_divide_by_5 = false;
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}
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if (use_divide_by_5) {
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if (_clkHZ > 6000000) {
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printWarn("Jtag probe limited to 6MHz");
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_clkHZ = 6000000;
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}
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} else {
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} else {
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if (_clkHZ > 30000000) {
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base_freq = 60000000;
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printWarn("Jtag probe limited to 30MHz");
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if ((ret = mpsse_store(DIS_DIV_5)) < 0)
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_clkHZ = 30000000;
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return ret;
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}
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}
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}
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presc = ((base_freq /_clkHZ) -1) / 2;
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if (_clkHZ > base_freq / 2) {
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real_freq = base_freq / ((1+presc)*2);
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printWarn("Jtag probe limited to %d MHz", base_freq / 2);
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_clkHZ = base_freq / 2;
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}
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presc = ((base_freq /_clkHZ) - 1) / 2;
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real_freq = base_freq / ((1 + presc) * 2);
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if (real_freq > _clkHZ)
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if (real_freq > _clkHZ)
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presc++;
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++presc;
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real_freq = base_freq / ((1+presc)*2);
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real_freq = base_freq / ((1+presc)*2);
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/* just to have a better display */
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/* just to have a better display */
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