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xilinx: lint more happy

This commit is contained in:
Gwenhael Goavec-Merou 2023-11-25 15:14:32 +01:00
parent 234f7f5a35
commit 8007ffe263
2 changed files with 40 additions and 40 deletions
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32
src/xilinx.cpp
View File

@ -7,29 +7,28 @@
#include <cstring> #include <cstring>
#include <iostream> #include <iostream>
#include <memory>
#include <stdexcept> #include <stdexcept>
#include <string> #include <string>
#include <vector> #include <vector>
#include <memory>
#include "jtag.hpp"
#include "bitparser.hpp" #include "bitparser.hpp"
#include "common.hpp" #include "common.hpp"
#include "configBitstreamParser.hpp" #include "configBitstreamParser.hpp"
#include "jedParser.hpp"
#include "mcsParser.hpp"
#include "spiFlash.hpp"
#include "rawParser.hpp"
#include "display.hpp" #include "display.hpp"
#include "spiInterface.hpp" #include "jedParser.hpp"
#include "xilinx.hpp" #include "jtag.hpp"
#include "xilinxMapParser.hpp" #include "mcsParser.hpp"
#include "part.hpp" #include "part.hpp"
#include "progressBar.hpp" #include "progressBar.hpp"
#if defined (_WIN64) || defined (_WIN32) #if defined (_WIN64) || defined (_WIN32)
#include "pathHelper.hpp" #include "pathHelper.hpp"
#endif #endif
#include "rawParser.hpp"
#include "spiFlash.hpp"
#include "spiInterface.hpp"
#include "xilinx.hpp"
#include "xilinxMapParser.hpp"
/* Used for xc3s */ /* Used for xc3s */
#define USER1 0x02 #define USER1 0x02
@ -195,7 +194,7 @@ static void open_bitfile(
#define FUSE_DNA 0x32 #define FUSE_DNA 0x32
unsigned long long Xilinx::fuse_dna_read(void) uint64_t Xilinx::fuse_dna_read(void)
{ {
unsigned char tx_data[8] = {0, 0, 0, 0, 0, 0, 0, 0}; unsigned char tx_data[8] = {0, 0, 0, 0, 0, 0, 0, 0};
unsigned char rx_data[8]; unsigned char rx_data[8];
@ -204,7 +203,7 @@ unsigned long long Xilinx::fuse_dna_read(void)
_jtag->shiftIR(FUSE_DNA, 6); _jtag->shiftIR(FUSE_DNA, 6);
_jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 64); _jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 64);
unsigned long long dna = 0; uint64_t dna = 0;
for(int i = 0; i < 8; i++) { for(int i = 0; i < 8; i++) {
unsigned char rev = 0; unsigned char rev = 0;
@ -217,7 +216,7 @@ unsigned long long Xilinx::fuse_dna_read(void)
return dna & 0x1ffffffffffffff; return dna & 0x1ffffffffffffff;
} }
unsigned int Xilinx::xadc_read(unsigned short addr) unsigned int Xilinx::xadc_read(uint16_t addr)
{ {
unsigned int tx_data = (1 << 26) | (addr << 16); unsigned int tx_data = (1 << 26) | (addr << 16);
unsigned int rx_data = 0; unsigned int rx_data = 0;
@ -232,7 +231,7 @@ unsigned int Xilinx::xadc_read(unsigned short addr)
return rx_data; return rx_data;
} }
void Xilinx::xadc_write(unsigned short addr, unsigned short data) void Xilinx::xadc_write(uint16_t addr, uint16_t data)
{ {
unsigned int tx_data = (1 << 26) | (addr << 16) | data; unsigned int tx_data = (1 << 26) | (addr << 16) | data;
unsigned int rx_data = 0; unsigned int rx_data = 0;
@ -242,7 +241,7 @@ void Xilinx::xadc_write(unsigned short addr, unsigned short data)
_jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 32); _jtag->shiftDR((unsigned char *)&tx_data, (unsigned char *)&rx_data, 32);
} }
unsigned int Xilinx::xadc_single(unsigned short ch) unsigned int Xilinx::xadc_single(uint16_t ch)
{ {
_jtag->go_test_logic_reset(); _jtag->go_test_logic_reset();
// single channel, disable the sequencer // single channel, disable the sequencer
@ -385,7 +384,7 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
if (read_dna) { if (read_dna) {
if (_fpga_family == ARTIX_FAMILY || _fpga_family == KINTEXUS_FAMILY) { if (_fpga_family == ARTIX_FAMILY || _fpga_family == KINTEXUS_FAMILY) {
unsigned long long dna = Xilinx::fuse_dna_read(); uint64_t dna = Xilinx::fuse_dna_read();
printf("{\"dna\": \"0x%016lx\"}\n", dna); printf("{\"dna\": \"0x%016lx\"}\n", dna);
} else { } else {
throw std::runtime_error("Error: read_xadc only supported for Artix 7"); throw std::runtime_error("Error: read_xadc only supported for Artix 7");
@ -955,7 +954,6 @@ bool Xilinx::xc3s_flow_program(ConfigBitstreamParser *bit)
_jtag->toggleClk(32); _jtag->toggleClk(32);
if (_jtag->shiftIR(BYPASS, _irlen) < 0) if (_jtag->shiftIR(BYPASS, _irlen) < 0)
return false; return false;
//data[0] = 0x00;
uint8_t d = 0; uint8_t d = 0;
if (_jtag->shiftDR(&d, NULL, 1) < 0) if (_jtag->shiftDR(&d, NULL, 1) < 0)
return false; return false;

22
src/xilinx.hpp
View File

@ -3,16 +3,18 @@
* Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com> * Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
*/ */
#ifndef XILINX_HPP #ifndef SRC_XILINX_HPP_
#define XILINX_HPP #define SRC_XILINX_HPP_
#include <map>
#include <string> #include <string>
#include <vector>
#include "configBitstreamParser.hpp" #include "configBitstreamParser.hpp"
#include "device.hpp" #include "device.hpp"
#include "jedParser.hpp"
#include "jtag.hpp" #include "jtag.hpp"
#include "spiInterface.hpp" #include "spiInterface.hpp"
#include "jedParser.hpp"
class Xilinx: public Device, SPIInterface { class Xilinx: public Device, SPIInterface {
public: public:
@ -145,11 +147,11 @@ class Xilinx: public Device, SPIInterface {
/*! /*!
* \brief prepare SPI flash access (need to have bridge in RAM) * \brief prepare SPI flash access (need to have bridge in RAM)
*/ */
virtual bool prepare_flash_access() override; bool prepare_flash_access() override;
/*! /*!
* \brief end of SPI flash access * \brief end of SPI flash access
*/ */
virtual bool post_flash_access() override; bool post_flash_access() override;
private: private:
/* list of xilinx family devices */ /* list of xilinx family devices */
@ -193,12 +195,12 @@ class Xilinx: public Device, SPIInterface {
}; };
/* XADC */ /* XADC */
unsigned int xadc_read(unsigned short addr); unsigned int xadc_read(uint16_t addr);
void xadc_write(unsigned short addr, unsigned short data); void xadc_write(uint16_t addr, uint16_t data);
unsigned int xadc_single(unsigned short ch); unsigned int xadc_single(uint16_t ch);
/* DNA */ /* DNA */
unsigned long long fuse_dna_read(void); uint64_t fuse_dna_read(void);
/*! /*!
* \brief Starting from UltraScale, Xilinx devices can support dual * \brief Starting from UltraScale, Xilinx devices can support dual
@ -223,4 +225,4 @@ class Xilinx: public Device, SPIInterface {
std::string _user_instruction; /* which USER bscan instruction to interface with SPI */ std::string _user_instruction; /* which USER bscan instruction to interface with SPI */
}; };
#endif #endif // SRC_XILINX_HPP_