luke
/
openFPGALoader
mirror of https://github.com/trabucayre/openFPGALoader.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

altera, xilinx: verbose mode

This commit is contained in:
Gwenhael Goavec-Merou 2019-11-21 09:26:43 +01:00
parent a973ab3a8c
commit 7d6f57dd9a
4 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
altera.cpp
View File

@ -7,8 +7,8 @@
#define IRLENGTH 10 #define IRLENGTH 10
#define BIT_FOR_FLASH "/usr/local/share/cycloader/test_sfl.svf" #define BIT_FOR_FLASH "/usr/local/share/cycloader/test_sfl.svf"
Altera::Altera(FtdiJtag *jtag, std::string filename):Device(jtag, filename), Altera::Altera(FtdiJtag *jtag, std::string filename, bool verbose):
_svf(_jtag) Device(jtag, filename, verbose), _svf(_jtag, _verbose)
{ {
if (_filename != "") { if (_filename != "") {
if (_file_extension == "svf") if (_file_extension == "svf")

2
altera.hpp
View File

@ -8,7 +8,7 @@
class Altera: public Device { class Altera: public Device {
public: public:
Altera(FtdiJtag *jtag, std::string filename); Altera(FtdiJtag *jtag, std::string filename, bool verbose);
~Altera(); ~Altera();
void program(unsigned int offset = 0); void program(unsigned int offset = 0);

14
xilinx.cpp
View File

@ -9,8 +9,9 @@
#include "xilinx.hpp" #include "xilinx.hpp"
#include "part.hpp" #include "part.hpp"
Xilinx::Xilinx(FtdiJtag *jtag, std::string filename):Device(jtag, filename) Xilinx::Xilinx(FtdiJtag *jtag, std::string filename, bool verbose):
{ Device(jtag, filename, verbose)
{
if (_filename != ""){ if (_filename != ""){
if (_file_extension == "bit") if (_file_extension == "bit")
_mode = Device::MEM_MODE; _mode = Device::MEM_MODE;
@ -43,7 +44,6 @@ void Xilinx::reset()
_jtag->shiftIR(BYPASS, 6); _jtag->shiftIR(BYPASS, 6);
_jtag->set_state(FtdiJtag::RUN_TEST_IDLE); _jtag->set_state(FtdiJtag::RUN_TEST_IDLE);
_jtag->toggleClk(2000); _jtag->toggleClk(2000);
} }
int Xilinx::idCode() int Xilinx::idCode()
@ -69,7 +69,7 @@ void Xilinx::program(unsigned int offset)
reset(); reset();
break; break;
case Device::MEM_MODE: case Device::MEM_MODE:
BitParser bitfile(_filename); BitParser bitfile(_filename, _verbose);
bitfile.parse(); bitfile.parse();
program_mem(bitfile, offset); program_mem(bitfile, offset);
break; break;
@ -82,14 +82,14 @@ void Xilinx::program_spi(unsigned int offset)
bitname += fpga_list[idCode()].family + ".bit"; bitname += fpga_list[idCode()].family + ".bit";
/* first: load spi over jtag */ /* first: load spi over jtag */
BitParser bitfile(bitname); BitParser bitfile(bitname, _verbose);
bitfile.parse(); bitfile.parse();
program_mem(bitfile, offset); program_mem(bitfile, offset);
/* last: read file and erase/flash spi flash */ /* last: read file and erase/flash spi flash */
McsParser mcs(_filename); McsParser mcs(_filename, _verbose);
mcs.parse(); mcs.parse();
SPIFlash spiFlash(_jtag); SPIFlash spiFlash(_jtag, _verbose);
spiFlash.erase_and_prog(offset, mcs.getData(), mcs.getLength()); spiFlash.erase_and_prog(offset, mcs.getData(), mcs.getLength());
} }

2
xilinx.hpp
View File

@ -7,7 +7,7 @@
class Xilinx: public Device { class Xilinx: public Device {
public: public:
Xilinx(FtdiJtag *jtag, std::string filename); Xilinx(FtdiJtag *jtag, std::string filename, bool verbose);
~Xilinx(); ~Xilinx();
void program(unsigned int offset = 0) override; void program(unsigned int offset = 0) override;