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spiOverJtag: add bitstream for ECP4CE15F23

This commit is contained in:
Gwenhael Goavec-Merou 2021-11-28 16:50:13 +01:00
parent 048ddecd38
commit 7ceaab0126
5 changed files with 4 additions and 3 deletions
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2
doc/compatibility/board.rst
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@ -49,7 +49,7 @@ Boards
nexysVideo `Digilent Nexys Video <https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start>`__ Artix xc7a200tsbg484 OK OK nexysVideo `Digilent Nexys Video <https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start>`__ Artix xc7a200tsbg484 OK OK
orangeCrab `Orange Crab <https://github.com/gregdavill/OrangeCrab>`__ ECP5 LFE5U-25F-8MG285C OK (JTAG) OK (DFU) orangeCrab `Orange Crab <https://github.com/gregdavill/OrangeCrab>`__ ECP5 LFE5U-25F-8MG285C OK (JTAG) OK (DFU)
pipistrello `Saanlima Pipistrello LX45 <http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello>`__ Spartan6 xc6slx45-csg324 OK OK pipistrello `Saanlima Pipistrello LX45 <http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello>`__ Spartan6 xc6slx45-csg324 OK OK
qmtechCycloneIV `QMTech CycloneIV Core Board <https://fr.aliexpress.com/item/32949281189.html>`__ Cyclone IV EP4CE15F23C8N OK NT qmtechCycloneIV `QMTech CycloneIV Core Board <https://fr.aliexpress.com/item/32949281189.html>`__ Cyclone IV EP4CE15F23C8N OK OK
qmtechCycloneV `QMTech CycloneV Core Board <https://fr.aliexpress.com/i/1000006622149.html>`__ Cyclone V 5CEFA2F23I7 OK OK qmtechCycloneV `QMTech CycloneV Core Board <https://fr.aliexpress.com/i/1000006622149.html>`__ Cyclone V 5CEFA2F23I7 OK OK
runber `SeeedStudio Gowin RUNBER <https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html>`__ littleBee GW1N-4 OK IF/EF runber `SeeedStudio Gowin RUNBER <https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html>`__ littleBee GW1N-4 OK IF/EF
runber `Scarab Hardware MiniSpartan6+ <https://www.kickstarter.com/projects/1812459948/minispartan6-a-powerful-fpga-board-and-easy-to-use>`__ Spartan6 xc6slx25-3-ftg256 OK NT runber `Scarab Hardware MiniSpartan6+ <https://www.kickstarter.com/projects/1812459948/minispartan6-a-powerful-fpga-board-and-easy-to-use>`__ Spartan6 xc6slx25-3-ftg256 OK NT

2
spiOverJtag/Makefile
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@ -4,7 +4,7 @@ XILINX_PARTS := xc6slx45csg324 xc6slx100fgg484 \
xc7s50csga324 xc7s50csga324
XILINX_BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(XILINX_PARTS))) XILINX_BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
ALTERA_PARTS := 10cl025256 ep4ce2217 5ce223 5ce423 ALTERA_PARTS := 10cl025256 ep4ce2217 ep4ce1523 5ce223 5ce423
ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS))) ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES) BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)

1
spiOverJtag/build.py
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@ -81,6 +81,7 @@ else:
full_part = { full_part = {
"10cl025256": "10CL025YU256C8G", "10cl025256": "10CL025YU256C8G",
"ep4ce2217" : "EP4CE22F17C6", "ep4ce2217" : "EP4CE22F17C6",
"ep4ce1523" : "EP4CE15F23C8",
"5ce223" : "5CEFA2F23I7", "5ce223" : "5CEFA2F23I7",
"5ce423" : "5CEBA4F23C8", "5ce423" : "5CEBA4F23C8",
"5cse423" : "5CSEMA4U23C6", "5cse423" : "5CSEMA4U23C6",

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spiOverJtag/spiOverJtag_ep4ce1523.rbf.gz Normal file
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2
src/board.hpp
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@ -136,7 +136,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("pipistrello", "xc6slx45csg324", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("pipistrello", "xc6slx45csg324", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT),
DFU_BOARD("orangeCrab", "", "dfu", 0x1209, 0x5af0, 0), DFU_BOARD("orangeCrab", "", "dfu", 0x1209, 0x5af0, 0),
JTAG_BOARD("qmtechCycloneIV", "", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("tangnano", "", "ch552_jtag", 0, 0, CABLE_DEFAULT), JTAG_BOARD("tangnano", "", "ch552_jtag", 0, 0, CABLE_DEFAULT),