altera: agilex3/agilex5 support draft (memory only)
This commit is contained in:
Gwenhael Goavec-Merou
parent
add9c95775
commit
764ce23f35
284
src/altera.cpp
284
src/altera.cpp
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@ -44,6 +44,10 @@ Altera::Altera(Jtag *jtag, const std::string &filename,
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std::string family = fpga_list[_idcode].family;
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if (family == "MAX 10") {
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_fpga_family = MAX10_FAMILY;
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} else if (family == "agilex 3") {
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_fpga_family = AGILEX3_FAMILY;
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} else if (family == "agilex 5") {
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_fpga_family = AGILEX5_FAMILY;
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} else {
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_fpga_family = CYCLONE_MISC; // FIXME
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}
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@ -242,6 +246,16 @@ void Altera::program(unsigned int offset, bool unprotect_flash)
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return;
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}
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/* Specific case for Agilex */
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if (_fpga_family == AGILEX3_FAMILY || _fpga_family == AGILEX5_FAMILY) {
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if (_mode != Device::MEM_MODE) {
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printError("Altera: Error Write to flash for Agilex not supported");
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return;
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}
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agilex_program();
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return;
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}
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/* in all case we consider svf is mandatory
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* MEM_MODE : svf file provided for constructor
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* is the bitstream to use
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@ -1010,6 +1024,276 @@ bool Altera::sectors_mask_start_end_addr(const Altera::max10_mem_t *mem,
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return true;
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}
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/* ---------------------------------- */
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/* Agilex 3/5 */
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/* ---------------------------------- */
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#define AGILEX_ISC_PROGRAM {0x02, 0x00}
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#define AGILEX_COMMAND {0x01, 0x02}
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#define AGILEX_ISC_SR {0x02, 0x02}
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#define AGILEX_IRFLOW {0x08, 0x02}
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#define AGILEX_BYPASS {0xff, 0x03}
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#define uintStarTo64(__input__) ( \
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(static_cast<uint64_t>(__input__[4]) << 32) | \
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(static_cast<uint64_t>(__input__[3]) << 24) | \
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(static_cast<uint64_t>(__input__[2]) << 16) | \
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(static_cast<uint64_t>(__input__[1]) << 8) | \
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(static_cast<uint64_t>(__input__[0]) << 0))
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#define DWORDToCharStar(__dword__) { \
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static_cast<unsigned char>((__dword__ >> 0) & 0xff), \
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static_cast<unsigned char>((__dword__ >> 8) & 0xff), \
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static_cast<unsigned char>((__dword__ >> 16) & 0xff), \
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static_cast<unsigned char>((__dword__ >> 24) & 0xff), \
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static_cast<unsigned char>((__dword__ >> 32) & 0xff) \
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}
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// Depends to the JTAG frequency?
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static uint32_t agilex_toggle_length = 16;
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bool Altera::agilex_poll_status(uint64_t *expected, uint64_t *mask,
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uint32_t check_len, int max_poll)
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{
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const uint8_t isc_sr[2] = AGILEX_ISC_SR;
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_jtag->shiftIR((unsigned char *)isc_sr, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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if (_verbose)
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printf("Begin\n");
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for (uint32_t check = 0; check < check_len; check++) {
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bool match = false;
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const uint64_t exp = expected[check];
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const uint64_t msk = mask[check];
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for (int i = 0; i < max_poll && !match; i++) {
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uint8_t status[5];
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_jtag->shiftDR(NULL, status, 34);
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_jtag->toggleClk(agilex_toggle_length);
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uint64_t res = uintStarTo64(status) & 0x3FFFFFFFF;
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if (_verbose) {
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printf("%2d/%3d: 0x%08lx 0x%08lx %08lx ", check, i,
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res, res & msk, exp & msk);
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for (int a = 0; a < 5; a++)
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printf("%02x ", status[a]);
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printf("\n");
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}
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// It's silly but mask must be applied to expected
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// too...
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match = ((res & msk) == (msk & exp));
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}
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if (!match)
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return false;
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}
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return true;
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}
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bool Altera::agilex_send_instruction(const uint8_t *cmd, const uint64_t *tx,
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uint64_t *rx, uint32_t length)
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{
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unsigned char rx_pkt[5];
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_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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if (!rx && !tx)
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return true;
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for (uint32_t i = 0; i < length; i++) {
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const uint64_t v = (tx) ? tx[i] : 0;
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const unsigned char tx_pkt[] = DWORDToCharStar(v);
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_jtag->shiftDR((tx)? tx_pkt : NULL, (rx) ? rx_pkt : NULL, 34);
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_jtag->toggleClk(agilex_toggle_length);
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if (rx)
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rx[i] = uintStarTo64(rx_pkt);
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}
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return true;
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}
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bool Altera::agilex_isc_init()
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{
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const uint8_t cmd[2] = AGILEX_COMMAND;
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/* Everything is magic here.
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* stp0 and step2 are constant for AGILEX3 and AGILEX5 (at least
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* with tested devices)
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* stp1 is partially constant: 3 Words changes between synthesis
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* (jam file) but if this value match the check everything is fine
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*/
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const uint64_t stp0[3] = {0x000000000, 0x300000000, 0x200000000};
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const uint64_t stp1[3] = {0x000000000, 0x1F0001001, 0x27E2DA938};
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const uint64_t stp2[2] = {0x000000000, 0x200000005};
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if (!agilex_send_instruction(cmd, stp0, NULL, 3)) {
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printError("Altera: Error during step0 write configuration");
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return false;
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}
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/* Again: magic words */
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uint64_t stp0_exp = 0x000000003;
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uint64_t stp0_mask = 0x3FDFFFFFD;
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if (!agilex_poll_status(&stp0_exp, &stp0_mask, 1)) {
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printf("Altera: STP0: poll failed\n");
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return false;
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}
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/* Device specific configuration */
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if (!agilex_send_instruction(cmd, stp1, NULL, 3)) {
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printError("Altera: Error during step0 write configuration");
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return false;
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}
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/* Again: magic words */
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uint64_t stp1_exp[] = {0x3C0004001, (0x3FFFFFFFF & ((stp1[2] << 2) | 0x03))};
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uint64_t stp1_mask[] = {0x3FDFFFFFD, 0x3FFFFFFFD};
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if (!agilex_poll_status(stp1_exp, stp1_mask, 2)) {
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printError("Altera: Error during Device specific configuration step");
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return false;
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}
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/* Enter ISC Configure mode */
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if (!agilex_send_instruction(cmd, stp2, NULL, 2)) {
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printError("Altera: Error during enter ISC Configure write");
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return false;
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}
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uint64_t stp2_exp = 0x000000003;
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uint64_t stp2_mask = 0x3FDFFFFFD;
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if (!agilex_poll_status(&stp2_exp, &stp2_mask, 1, 300)) {
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printError("Error during ISC configure mode");
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return false;
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}
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return true;
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}
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bool Altera::agilex_exit_and_conf_done()
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{
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const uint8_t cmd[2] = AGILEX_COMMAND;
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const uint8_t sr[2] = AGILEX_ISC_SR;
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const uint8_t bypass[2] = AGILEX_BYPASS;
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const uint8_t done0[5] = {0x00, 0x00, 0x00, 0x00, 0x00};
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const uint8_t done1[5] = {0x04, 0x00, 0x00, 0x00, 0x02};
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_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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_jtag->shiftDR((unsigned char *)done0, NULL, 34);
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_jtag->toggleClk(agilex_toggle_length);
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_jtag->shiftDR((unsigned char *)done1, NULL, 34);
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_jtag->toggleClk(agilex_toggle_length);
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_jtag->shiftIR((unsigned char *)sr, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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uint8_t stat_tx[5];
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uint8_t stat_rx[5];
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memset(stat_tx, 0, 5);
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uint64_t status;
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do {
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_jtag->shiftDR((unsigned char *)stat_tx, stat_rx, 34);
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_jtag->toggleClk(agilex_toggle_length);
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status = uintStarTo64(stat_rx);
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} while ((status & 0x01) != 0);
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_jtag->shiftIR((unsigned char *)bypass, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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return true;
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}
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bool Altera::agilex_load_bitstream(const uint8_t *data, const uint32_t length)
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{
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const uint8_t stat_cmd[2] = AGILEX_IRFLOW;
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const uint8_t cmd[2] = AGILEX_ISC_PROGRAM;
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const uint8_t start[5] = {0x07, 0x00, 0x00, 0x00, 0x00};
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const uint32_t xfer_min_length = 4096;
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const uint32_t xfer_max_length = 65536;
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uint8_t buffer[xfer_max_length + 9];
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buffer[0] = 0xff;
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buffer[1] = 0xff;
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buffer[2] = 0xff;
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buffer[3] = 0xff;
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buffer[4] = 0x00;
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buffer[5] = 0x2a;
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buffer[6] = 0x7e;
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buffer[7] = 0xa1;
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uint8_t *ptr = &buffer[8];
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/* Pre command */
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_jtag->shiftIR((unsigned char *)stat_cmd, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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_jtag->shiftDR((unsigned char *)start, NULL, 34);
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_jtag->toggleClk(agilex_toggle_length);
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uint32_t wr_pos = 0;
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uint32_t curr_xfer_len = xfer_min_length;
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ProgressBar progress("Load SRAM", length, 50, false);
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while (wr_pos < length) {
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uint32_t xfer_len = std::min(curr_xfer_len, length - wr_pos);
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memcpy(ptr, &data[wr_pos], xfer_len);
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ptr[xfer_len] = 0;
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_jtag->shiftIR((unsigned char *)cmd, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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_jtag->shiftDR((unsigned char *)buffer, NULL, 64 + 1 + xfer_len * 8);
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_jtag->toggleClk(agilex_toggle_length);
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/* loop until status bit0 low */
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uint8_t stat_tx[5] = {0x00, 0x00, 0x00, 0x00, 0x00};
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uint8_t stat_rx[5];
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uint64_t res;
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bool busy, error;
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do {
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_jtag->shiftIR((unsigned char *)stat_cmd, NULL, IRLENGTH);
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_jtag->toggleClk(agilex_toggle_length);
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_jtag->shiftDR((unsigned char *)stat_tx, stat_rx, 37);
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_jtag->toggleClk(agilex_toggle_length);
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res = uintStarTo64(stat_rx);
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busy = ((res >> 0) & 0x01);
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error = ((res >> 1) & 0x01);
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if (error) {
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progress.fail();
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printError("Device Configuration Error");
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return false;
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}
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stat_tx[0] = 0x01;
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} while(busy);
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const uint32_t offset_after_write = wr_pos + curr_xfer_len;
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// next position is provided by the FPGA
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// it's a x 4
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wr_pos = res & (~0x03);
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/* search if we have to increase or reduce curr_xfer_len */
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if (offset_after_write == wr_pos)
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curr_xfer_len = std::min(curr_xfer_len * 2, xfer_max_length);
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else
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curr_xfer_len = std::max(curr_xfer_len / 2, xfer_min_length);
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progress.display(wr_pos);
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}
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progress.done();
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return true;
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}
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bool Altera::agilex_program()
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{
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RawParser rbf(_filename, _verbose);
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rbf.parse();
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const uint32_t rbf_length = rbf.getLength() / 8;
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const uint8_t *rbf_data = rbf.getData();
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if (!agilex_isc_init())
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return false;
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if (!agilex_load_bitstream(rbf_data, rbf_length))
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return false;
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if (!agilex_exit_and_conf_done())
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return false;
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return true;
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}
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/* SPI interface */
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int Altera::spi_put(uint8_t cmd, const uint8_t *tx, uint8_t *rx, uint32_t len)
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@ -90,10 +90,25 @@ class Altera: public Device, FlashInterface {
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MAX10_FAMILY = 1,
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CYCLONE5_FAMILY = 2,
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CYCLONE10_FAMILY = 3,
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STRATIXV_FAMILY = 3,
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STRATIXV_FAMILY = 4,
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AGILEX3_FAMILY = 5,
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AGILEX5_FAMILY = 6,
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CYCLONE_MISC = 10, // Fixme: idcode shared
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UNKNOWN_FAMILY = 999
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};
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/**************************/
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/* agilex specific */
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/**************************/
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bool agilex_poll_status(uint64_t *expected, uint64_t *mask, uint32_t check_len,
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int max_poll=50);
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bool agilex_send_instruction(const uint8_t *cmd, const uint64_t *tx,
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uint64_t *rx, uint32_t length);
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bool agilex_isc_init();
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bool agilex_exit_and_conf_done();
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bool agilex_load_bitstream(const uint8_t *data, const uint32_t length);
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bool agilex_program();
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/*************************/
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/* max10 specific */
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/*************************/
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