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spiOverJtag: Remove obsolete xc6 directory

This commit is contained in:
Uwe Bonnes 2024-02-28 12:04:46 +01:00
parent a926ab9b88
commit 75e086cd55
5 changed files with 0 additions and 129 deletions
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5
spiOverJtag/xc6/.gitignore vendored
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*
!*.gitignore
!*.ucf
!*.vhd
!*.tcl

6
spiOverJtag/xc6/constr_xc6s_fgg484.ucf
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CONFIG VCCAUX = "2.5";
NET "sdo" LOC = AA20 | IOSTANDARD = LVCMOS33;
NET "sdi" LOC = AB20 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = T5 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = Y21 | IOSTANDARD = LVCMOS33;

6
spiOverJtag/xc6/constr_xc6slx9_tqg144.ucf
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CONFIG VCCAUX = "2.5";
NET "sdo" LOC = P65 | IOSTANDARD = LVCMOS33;
NET "sdi" LOC = P64 | IOSTANDARD = LVCMOS33;
NET "csn" LOC = P38 | IOSTANDARD = LVCMOS33;
NET "sck" LOC = P70 | IOSTANDARD = LVCMOS33;

44
spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl
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#
# Project automation script for spiOverJtag_xc6
#
# Created for ISE version 14.7
#
set myProject "xilinx_spiOverJtag_xc6"
set myScript "xilinx_spiOverJtag_xc6.tcl"
puts "\n$myScript: Rebuilding ($myProject)...\n"
if { [file exists "${myProject}.xise" ] } {
project open $myProject
} else {
project new $myProject
project set family "Spartan6"
project set device "xc6slx100"
project set package "fgg484"
project set speed "-2"
project set top_level_module_type "HDL"
project set synthesis_tool "XST (VHDL/Verilog)"
project set simulator "ISim (VHDL/Verilog)"
project set "Preferred Language" "VHDL"
project set "Enable Message Filtering" "false"
project set "VHDL Source Analysis Standard" "VHDL-200X"
project set "Enable Internal Done Pipe" "true" -process "Generate Programming File"
xfile add "constr_xc6s_fgg484.ucf"
xfile add "xilinx_spiOverJtag_xc6.vhd"
project set top "bhv" "xilinx_spiOverJtag"
}
if { ! [ process run "Implement Design" ] } {
return false;
}
if { ! [ process run "Generate Programming File" ] } {
return false;
}
puts "Run completed successfully."
project close

68
spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity xilinx_spiOverJtag is
port (
csn : out std_logic;
sdi : out std_logic;
sdo : in std_logic;
sck : out std_logic;
wpn : out std_logic;
hldn : out std_logic
);
end entity xilinx_spiOverJtag;
architecture bhv of xilinx_spiOverJtag is
signal capture, drck, sel, shift, update : std_logic;
signal runtest : std_logic;
signal tdi, tdo : std_logic;
signal fsm_csn : std_logic;
signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic;
begin
wpn <= '1';
hldn <= '1';
-- jtag -> spi flash
csn <= fsm_csn;
sdi <= tdi;
tdo <= tdi when (sel) = '0' else sdo;
sck <= drck;
tmp_cap_s <= capture and sel;
tmp_up_s <= update and sel;
process(drck, runtest) begin
if runtest = '1' then
fsm_csn <= '1';
elsif rising_edge(drck) then
if tmp_cap_s = '1' then
fsm_csn <= '0';
elsif tmp_up_s = '1' then
fsm_csn <= '1';
else
fsm_csn <= fsm_csn;
end if;
end if;
end process;
BSCAN_SPARTAN6_inst : BSCAN_SPARTAN6
generic map (
JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4).
)
port map (
CAPTURE => capture, -- 1-bit output: CAPTURE output from TAP controller.
DRCK => drck, -- 1-bit output: Data register output for USER functions.
RUNTEST => runtest, -- 1-bit output: Output signal that gets asserted when TAP controller is in Run Test
-- Idle state.
SEL => sel, -- 1-bit output: USER active output.
SHIFT => shift, -- 1-bit output: SHIFT output from TAP controller.
TDI => tdi, -- 1-bit output: TDI output from TAP controller.
UPDATE => update, -- 1-bit output: UPDATE output from TAP controller
TDO => tdo -- 1-bit input: Data input for USER function.
);
end architecture bhv;