Add support for Artix A7 15t

Tested on real hardware, connecting through Linux gpiod

spiOverJtag/Makefile

@@ -3,7 +3,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xc6slx16ftg256 xc6slx16csg324 xc6slx25csg324 xc6slx45csg324 xc6slx100fgg484 \
 	xc6slx25tcsg324 xc6slx45tfgg484 xc6slx150tfgg484 xc6slx150tcsg484 \
 	xc6vlx130tff784 \
-	xc7a15tcpg236 \
+	xc7a15tcpg236 xc7a15tfgg484 \
 	xc7a25tcpg238 xc7a25tcsg325 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \
 	xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a50tcsg325 xc7a75tfgg484 \

spiOverJtag/build.py

@@ -90,6 +90,7 @@ if tool in ["ise", "vivado"]:
         "xc6slx150tfgg484" : "xc6s_t_fgg484",
         "xc6vlx130tff784"  : "xc6v_ff784",
         "xc7a15tcpg236"    : "xc7a_cpg236",
+        "xc7a15tfgg484"    : "xc7a_fgg484",
         "xc7a25tcpg238"    : "xc7a_cpg238",
         "xc7a25tcsg325"    : "xc7a_csg325",
         "xc7a35tcpg236"    : "xc7a_cpg236",

spiOverJtag/xilinx_spiOverJtag.tcl

@@ -7,6 +7,7 @@ file delete -force $build_path
 
 # Project creation
 set grade [dict create \
+	xc7a15tfgg484  -1 \
 	xc7a25tcpg238  -1 \
 	xc7a25tcsg325  -1 \
 	xc7a35tcpg236  -1 \
@@ -33,6 +34,7 @@ set pkg_name [dict create \
 	xc7a35tftg256  xc7a_ftg256 \
 	xc7a50tcpg236  xc7a_cpg236 \
 	xc7a50tcsg325  xc7a_csg325 \
+	xc7a15tfgg484  xc7a_fgg484 \
 	xc7a75tfgg484  xc7a_fgg484 \
 	xc7a100tfgg484 xc7a_fgg484 \
 	xc7a200tsbg484 xc7a_sbg484 \

src/part.hpp

@@ -76,6 +76,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x8424a093, {"xilinx", "virtex6", "xc6vlx130t", 10}},
 
 	/* Xilinx 7-Series / Artix7 */
+	{0x0362e093, {"xilinx", "artix a7 15t",  "xc7a15",  6}},
 	{0x037c2093, {"xilinx", "artix a7 25t",  "xc7a25",  6}},
 	{0x0362D093, {"xilinx", "artix a7 35t",  "xc7a35",  6}},
 	{0x0362c093, {"xilinx", "artix a7 50t",  "xc7a50t", 6}},