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Merge pull request #553 from cheyao/master 

Add support for icepi zero
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Gwenhael Goavec-Merou 2025-05-23 07:27:18 +02:00 committed by GitHub
parent f08454926a 7c423c15fd
commit 6c4dbe94cc
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7
doc/boards.yml
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@ -481,6 +481,13 @@
Flash: AS Flash: AS
Constraints: IceZumAlhambraII Constraints: IceZumAlhambraII
- ID: icepi-zero
Description: Icepi Zero
URL: https://github.com/cheyao/icepi-zero
FPGA: ECP5 LFE5U
Memory: OK
Flash: OK
- ID: kc705 - ID: kc705
Description: Xilinx KC705 Description: Xilinx KC705
URL: https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html URL: https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html

2
src/board.hpp
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@ -179,6 +179,8 @@ static std::map <std::string, target_board_t> board_list = {
DBUS4, DBUS0, DBUS1, DBUS2, DBUS4, DBUS0, DBUS1, DBUS2,
0, 0, CABLE_DEFAULT), 0, 0, CABLE_DEFAULT),
DFU_BOARD("icebreaker-bitsy", "", "dfu", 0x1d50, 0x6146, 0), DFU_BOARD("icebreaker-bitsy", "", "dfu", 0x1d50, 0x6146, 0),
JTAG_BITBANG_BOARD("icepi-zero", "", "ft231X", 0, 0,
FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS, CABLE_DEFAULT),
JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kcu105", "xcku040-ffva1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kcu105", "xcku040-ffva1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kcu116", "xcku5p-ffvb676", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kcu116", "xcku5p-ffvb676", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),