Merge pull request #320 from AEW2015/master

Artix+ AU25P support for Opal Kelly Board

src/part.hpp

@@ -65,6 +65,8 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},
 	{0x23731093, {"xilinx", "zynq",     "xc7z045", 6}},
 
+	{0x04A64093, {"xilinx", "artixusp", "xcau25p", 6}},
+
 	{0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 18}},
 	{0x14b79093, {"xilinx", "virtexusp", "xcvu37p", 18}},
 

src/xilinx.cpp

@@ -196,6 +196,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_fpga_family = KINTEX_FAMILY;
 	} else if (family == "kintexus") {
 		_fpga_family = KINTEXUS_FAMILY;
+	} else if (family == "artixusp") {
+		_fpga_family = ARTIXUSP_FAMILY;
 	} else if (family == "virtexusp") {
 		_fpga_family = VIRTEXUSP_FAMILY;
 		_ircode_map = ircode_mapping.at("virtexusp");

src/xilinx.hpp

@@ -163,6 +163,7 @@ class Xilinx: public Device, SPIInterface {
 			ZYNQ_FAMILY,
 			ZYNQMP_FAMILY,
 			XCF_FAMILY,
+			ARTIXUSP_FAMILY,
 			VIRTEXUSP_FAMILY,
 			UNKNOWN_FAMILY  = 999
 		};