mirror of
https://github.com/trabucayre/openFPGALoader.git
synced 2026-08-31 02:07:14 +02:00
initial commit
This commit is contained in:
Gwenhael Goavec-Merou
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/*
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* Copyright (C) 2019 Gwenhael Goavec-Merou <[email protected]>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <argp.h>
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#include <fstream>
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#include <iostream>
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#include <map>
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#include <sstream>
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#include <string.h>
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#include <unistd.h>
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#include <vector>
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#include "board.hpp"
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#include "cable.hpp"
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#include "device.hpp"
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#include "part.hpp"
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#include "epcq.hpp"
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#include "ftdipp_mpsse.hpp"
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#include "ftdijtag.hpp"
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#include "svf_jtag.hpp"
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#include "bitparser.hpp"
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#include "xilinx.hpp"
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#define BIT_FOR_FLASH "/usr/local/share/cycloader_prog/test_sfl.svf"
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enum {
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BIT_FORMAT = 1,
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SVF_FORMAT,
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RPD_FORMAT
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} _file_format;
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using namespace std;
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struct arguments {
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bool verbose, display, reset;
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unsigned int offset;
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string bit_file;
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string cable;
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string board;
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};
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const char *argp_program_version = "cycloader 1.0";
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const char *argp_program_bug_address = "<[email protected]>";
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static char doc[] = "cycloader -- a program to flash cyclone10 LP FPGA";
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static char args_doc[] = "BIT_FILE";
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static error_t parse_opt(int key, char *arg, struct argp_state *state);
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static struct argp_option options[] = {
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{"cable", 'c', "CABLE", 0, "jtag interface"},
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{"board", 'b', "BOARD", 0, "board name, may be used instead of cable"},
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{"display", 'd', 0, 0, "display FPGA and EEPROM model"},
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{"offset", 'o', "OFFSET", 0, "start offset in EEPROM"},
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{"verbose", 'v', 0, 0, "Produce verbose output"},
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{"reset", 'r', 0, 0, "reset FPGA after operations"},
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{0}
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};
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static struct argp argp = { options, parse_opt, args_doc, doc };
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void reset_fpga(FtdiJtag *jtag)
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{
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/* PULSE_NCONFIG */
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unsigned char tx_buff[4] = {0x01, 0x00};
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tx_buff[0] = 0x01;
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tx_buff[1] = 0x00;
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jtag->set_state(FtdiJtag::TEST_LOGIC_RESET);
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jtag->shiftIR(tx_buff, NULL, 10);
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jtag->toggleClk(1);
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jtag->set_state(FtdiJtag::TEST_LOGIC_RESET);
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}
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int main(int argc, char **argv)
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{
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FTDIpp_MPSSE::mpsse_bit_config cable;
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bool prog_mem = false, prog_eeprom = false;
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/* EEPROM must have reverse order
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* other flash (softcore binary) must have direct order
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*/
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bool reverse_order=true;
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short file_format = 0;
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/* command line args. */
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struct arguments args = {false, false, false, 0, "-", "-", "-"};
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/* parse arguments */
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argp_parse(&argp, argc, argv, 0, 0, &args);
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/* if a bit_file is provided check type using file extension */
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if (args.bit_file[0] != '-') {
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string file_extension = args.bit_file.substr(args.bit_file.find_last_of(".") + 1);
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if(file_extension == "svf") {
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/* svf file */
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prog_mem = true;
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file_format = SVF_FORMAT;
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} else if(file_extension == "rpd") {
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/* rdp file */
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prog_eeprom = true;
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args.reset = true; // FPGA must reload eeprom content
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file_format = RPD_FORMAT;
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} else if (file_extension == "bit") {
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prog_mem = true;
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file_format = BIT_FORMAT;
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} else {
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if (args.offset == 0) {
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cout << args.bit_file << " not FPGA bit make no sense to flash at beginning" << endl;
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return EXIT_FAILURE;
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}
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reverse_order = false;
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}
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}
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/* To have access to eeprom, an svf file must be send to memory
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* so we must reset FPGA if no other bitfile is sent.
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*/
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if (args.display && !prog_mem)
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args.reset = true;
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printf("%s svf:%s eeprom:%s\n", args.bit_file.c_str(), (prog_mem)?"true":"false",
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(prog_eeprom)?"true":"false");
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if (args.reset && prog_mem) {
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cerr << "Error: using both flash to RAM and reset make no sense" << endl;
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return EXIT_FAILURE;
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}
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/* if a board name is specified try to use this to determine cable */
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if (args.board[0] != '-' && board_list.find(args.board) != board_list.end()) {
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auto t = cable_list.find(board_list[args.board]);
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if (t == cable_list.end()) {
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cerr << "Error: interface "<< board_list[args.board];
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cerr << " for board " << args.board << " is not supported" << endl;
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return 1;
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}
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args.cable = (*t).first;
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} else if (args.cable[0] == '-') { /* if no board and no cable */
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cout << "No cable or board specified: using direct ft2232 interface" << endl;
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args.cable = "ft2232";
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}
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auto select_cable = cable_list.find(args.cable);
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if (select_cable == cable_list.end()) {
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cerr << "error : " << args.cable << " not found" << endl;
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return EXIT_FAILURE;
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}
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cable = select_cable->second;
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printf("%x %x\n", cable.pid, cable.vid);
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/* jtag base */
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FtdiJtag *jtag = new FtdiJtag(cable, 1, 6000000);
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/* SVF logic */
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SVF_jtag *svf = new SVF_jtag(jtag);
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/* epcq */
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EPCQ epcq(cable.vid, cable.pid, 2, 6000000);
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/* chain detection:
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* GGM TODO: must be done before
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*/
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vector<int> listDev;
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int found = jtag->detectChain(listDev, 5);
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int idcode = listDev[0];
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printf("found %d devices\n", found);
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if (found > 1) {
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cerr << "currently only one device is supported" << endl;
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return EXIT_FAILURE;
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}
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printf("%x\n", idcode);
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if (fpga_list.find(idcode) == fpga_list.end()) {
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cout << "Error: device not supported" << endl;
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return 1;
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} else {
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printf("idcode 0x%x\nfunder %s\nmodel %s\nfamily %s\n",
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idcode,
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fpga_list[idcode].funder.c_str(),
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fpga_list[idcode].model.c_str(),
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fpga_list[idcode].family.c_str());
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}
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string fab = fpga_list[idcode].funder;
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/* display fpga and eeprom */
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if (args.display) {
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vector<int> listDev;
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int found = jtag->detectChain(listDev, 5);
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printf("found %d devices\n", found);
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for (unsigned int z=0; z < listDev.size(); z++)
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printf("%x\n", listDev[z]);
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printf("\n\n");
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svf->parse(BIT_FOR_FLASH);
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printf("%x\n", epcq.detect());
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}
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if (prog_mem) {
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if (file_format == SVF_FORMAT) {
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svf->parse(args.bit_file);
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} else {
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printf("todo\n");
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Xilinx xil(jtag, Device::MEM_MODE, args.bit_file);
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printf("%x\n", xil.idCode());
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xil.program();
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//xil.reset();
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}
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} else if (prog_eeprom) {
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svf->parse(BIT_FOR_FLASH);
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epcq.program(args.offset, args.bit_file, reverse_order);
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}
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if (args.reset) {
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if (fab == "xilinx") {
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Xilinx xil(jtag, Device::NONE_MODE, "");
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xil.reset();
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} else {
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reset_fpga(jtag);
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}
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}
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}
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/* arguments parser */
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static error_t parse_opt(int key, char *arg, struct argp_state *state)
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{
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struct arguments *arguments = (struct arguments *)state->input;
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switch (key) {
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case 'r':
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arguments->reset = true;
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break;
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case 'd':
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arguments->display = true;
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break;
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case 'v':
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arguments->verbose = true;
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break;
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case 'o':
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arguments->offset = strtoul(arg, NULL, 16);
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break;
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case 'c':
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arguments->cable = arg;
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break;
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case 'b':
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arguments->board = arg;
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break;
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case ARGP_KEY_ARG:
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arguments->bit_file = arg;
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break;
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case ARGP_KEY_END:
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break;
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default:
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return ARGP_ERR_UNKNOWN;
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}
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return 0;
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}
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