Add ID and spiOverJtag bitstream for Stratix V GS D5

doc/FPGAs.yml

@@ -109,6 +109,13 @@ Intel:
     Memory: OK
     Flash: NT
   
+  - Description: Stratix V GS
+    Model:
+      - 5SGSD5
+    URL: https://www.intel.de/content/www/de/de/products/sku/210318/stratix-v-5sgsd5-fpga/specifications.html
+    Memory: OK
+    Flash: OK
+
   - Description: Cyclone 10 LP
     Model: 10CL025
     URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html

spiOverJtag/Makefile

@@ -22,7 +22,7 @@ XILINX_PARTS := xc3s500evq100 \
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
 ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
-	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927
+	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927 5sgsd5
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
 
 EFINIX_PARTS := t8f81 t13f256 ti180j484

spiOverJtag/altera_spiOverJtag.v

@@ -19,6 +19,8 @@ module spiOverJtag ();
 		.INTENDED_DEVICE_FAMILY  ("Cyclone IV E"),
 `elsif cyclonev
 		.INTENDED_DEVICE_FAMILY  ("Cyclone V"),
+`elsif stratixv
+		.INTENDED_DEVICE_FAMILY  ("Stratix V"),
 `endif
 		.ENHANCED_MODE           (1),
 		.ENABLE_SHARED_ACCESS    ("ON"),

spiOverJtag/build.py

@@ -32,6 +32,11 @@ elif subpart[0:2] == '5c':
     tool = "quartus"
     files.append({'name': currDir + 'constr_cycloneV.tcl',
                   'file_type': 'tclSource'})
+elif subpart[0:2] == '5s':
+    family = "Stratix V"
+    tool = "quartus"
+    files.append({'name': currDir + 'constr_cycloneV.tcl',
+                  'file_type': 'tclSource'})
 elif subpart == "xc7a":
     family = "Artix"
     tool = "vivado"
@@ -204,7 +209,8 @@ else:
         "5ce423"     : "5CEBA4F23C8",
         "5ce927"     : "5CEBA9F27C7",
         "5cse423"    : "5CSEMA4U23C6",
-        "5cse623"    : "5CSEBA6U23I7"}[part]
+        "5cse623"    : "5CSEBA6U23I7",
+        "5sgsd5"     : "5SGSMD5K2F40I3"}[part]
     files.append({'name': currDir + 'altera_spiOverJtag.v',
                   'file_type': 'verilogSource'})
     files.append({'name': currDir + 'altera_spiOverJtag.sdc',

src/part.hpp

@@ -206,6 +206,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x020f30dd, {"altera", "cyclone 10 LP", "10CL025", 10}},
 	{0x020f50dd, {"altera", "cyclone 10 LP", "10CL055", 10}},
 
+	/* Altera Stratix V */
+	{0x029070dd, {"altera", "stratix V GS", "5SGSD5", 10}},
+
 	/**************************************************************************/
 	/*                             Efinix                                     */
 	/**************************************************************************/