Add ID and spiOverJtag bitstream for Stratix V GS D5

2026-08-30 01:48:50 +02:00 · 2024-10-10 19:59:31 +02:00
parent 773a7c805d
commit 43fcc6ce2c
6 changed files with 20 additions and 2 deletions
@@ -206,6 +206,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x020f30dd, {"altera", "cyclone 10 LP", "10CL025", 10}},
 	{0x020f50dd, {"altera", "cyclone 10 LP", "10CL055", 10}},

+	/* Altera Stratix V */
+	{0x029070dd, {"altera", "stratix V GS", "5SGSD5", 10}},
+
 	/**************************************************************************/
 	/*                             Efinix                                     */
 	/**************************************************************************/