Add ID and spiOverJtag bitstream for Stratix V GS D5

This commit is contained in:
Andreas Galauner
2024-10-10 19:59:31 +02:00
parent 773a7c805d
commit 43fcc6ce2c
6 changed files with 20 additions and 2 deletions
+7
View File
@@ -108,6 +108,13 @@ Intel:
URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
Memory: OK
Flash: NT
- Description: Stratix V GS
Model:
- 5SGSD5
URL: https://www.intel.de/content/www/de/de/products/sku/210318/stratix-v-5sgsd5-fpga/specifications.html
Memory: OK
Flash: OK
- Description: Cyclone 10 LP
Model: 10CL025