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Merge pull request #91 from ultraembedded/master 

Added a couple more Spartan6 parts, and a Spartan6 board
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Gwenhael Goavec-Merou 2021-06-14 07:16:55 +02:00 committed by GitHub
parent 2bf7b255b3 470f2a2b25
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3 changed files with 5 additions and 1 deletions
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3
README.md
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@ -28,6 +28,7 @@ __Current supported kits:__
* [QMTech CycloneV Core Board](https://fr.aliexpress.com/i/1000006622149.html) (memory) * [QMTech CycloneV Core Board](https://fr.aliexpress.com/i/1000006622149.html) (memory)
* [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM) (memory and flash) * [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM) (memory and flash)
* [Saanlima Pipistrello LX45](http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello) (memory) * [Saanlima Pipistrello LX45](http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello) (memory)
* [Scarab Hardware MiniSpartan6+ (Spartan 6 LX9)](https://www.kickstarter.com/projects/1812459948/minispartan6-a-powerful-fpga-board-and-easy-to-use) (memory)
* [SeeedStudio Gowin RUNBER](https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html) (memory and flash) * [SeeedStudio Gowin RUNBER](https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html) (memory and flash)
* [SeeedStudio Spartan Edge Accelerator Board](http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board) (memory) * [SeeedStudio Spartan Edge Accelerator Board](http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board) (memory)
* [Sipeed Tang Nano](https://tangnano.sipeed.com/en/) (memory) * [Sipeed Tang Nano](https://tangnano.sipeed.com/en/) (memory)
@ -52,7 +53,7 @@ __Supported (tested) FPGA:__
* Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash) * Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash)
* Xilinx Kintex 7 [xc7k325t](https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable) (SRAM) * Xilinx Kintex 7 [xc7k325t](https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable) (SRAM)
* Xilinx Artix 7 [xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory and spi flash) * Xilinx Artix 7 [xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory and spi flash)
* Xilinx Spartan 6 [xc6slx25, xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) * Xilinx Spartan 6 [xc6slx9, xc6slx16, xc6slx25, xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory)
* Xilinx Spartan 7 [xc7s15, xc7s25, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50)) * Xilinx Spartan 7 [xc7s15, xc7s25, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50))
* Intel Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) (memory) * Intel Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) (memory)
* Intel Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) (memory. See note below) * Intel Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) (memory. See note below)

1
src/board.hpp
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@ -113,6 +113,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("littleBee", "", "ft2232", 0, 0), JTAG_BOARD("littleBee", "", "ft2232", 0, 0),
JTAG_BOARD("spartanEdgeAccelBoard", "", "",0, 0), JTAG_BOARD("spartanEdgeAccelBoard", "", "",0, 0),
JTAG_BOARD("pipistrello", "", "ft2232", 0, 0), JTAG_BOARD("pipistrello", "", "ft2232", 0, 0),
JTAG_BOARD("minispartan6", "", "ft2232", 0, 0),
JTAG_BOARD("qmtechCycloneV", "", "", 0, 0), JTAG_BOARD("qmtechCycloneV", "", "", 0, 0),
JTAG_BOARD("runber", "", "ft232", 0, 0), JTAG_BOARD("runber", "", "ft232", 0, 0),
JTAG_BOARD("tangnano", "", "ft2232", 0, 0), JTAG_BOARD("tangnano", "", "ft2232", 0, 0),

2
src/part.hpp
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@ -22,6 +22,8 @@ static std::map <int, fpga_model> fpga_list = {
{0x43651093, {"xilinx", "kintex7", "xc7k325t", 6}}, {0x43651093, {"xilinx", "kintex7", "xc7k325t", 6}},
{0x24001093, {"xilinx", "spartan6", "xc6slx9", 6}},
{0x24002093, {"xilinx", "spartan6", "xc6slx16", 6}},
{0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}}, {0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}},
{0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}}, {0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}},
{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}}, {0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}},